A low-voltage low-power analog memory cell with built-in 4-quadrant multiplication

An accurate switched-current (SI) memory cell and suitable for low-voltage low-power (LVLP) applications is proposed. Information is memorized as the gate-voltage of the input transistor, in a tunable gain-boosting triode-transconductor. Additionally, four-quadrant multiplication between the input voltage to the transconductor regulation-amplifier (X-operand) and the stored voltage (Y-operand) is provided. A simplified 2 x 2-memory array was prototyped according to a standard 0.8 mum n-well CMOS process and 1.8-V supply. Measured current-reproduction error is less than 0.26% for 0.25 muA less than or equal to I-SAMPLE less than or equal to 0.75 muA. Standby consumption is 6.75 muW per cell @I-SAMPLE = 0.75 muA. At room temperature, leakage-rate is 1.56 nA/ms. Four-quadrant multiplier (4QM) full-scale operands are 2x(max) = 320 mV(pp) and 2y(max). = 448 mV(pp), yielding a maximum output swing of 0.9 muA(pp). 4QM worst-case nonlinearity is 7.9%.

An accurate low-voltage analog memory-cell with built-in multiplication

A CMOS memory-cell for dynamic storage of analog data and suitable for LVLP applications is proposed. Information is memorized as the gate-voltage of input-transistor of a gain-boosting triode-transconductor. The enhanced output-resistance improves accuracy on reading out the sampled currents. Additionally, a four-quadrant multiplication between the input to regulation-amplifier of the transconductor and the stored voltage is provided. Designing complies with a low-voltage 1.2μm N-well CMOS fabrication process. For a 1.3V-supply, CCELL=3.6pF and sampling interval is 0.25μA≤ ISAMPLE ≤ 0.75μA. The specified retention time is 1.28ms and corresponds to a charge-variation of 1% due to junction leakage @75°C. A range of MR simulations confirm circuit performance. Absolute read-out error is below O.40% while the four-quadrant multiplier nonlinearity, at full-scale is 8.2%. Maximum stand-by consumption is 3.6μW/cell.

Neonatal anoxia in rats: hippocampal cellular and subcellular changes related to cell death and spatial memory

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

A transactional runtime system for the Cell/BE architecture

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Proteins of Leishmania (Viannia) shawi confer protection associated with Th1 immune response and memory generation

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Gestational protein restriction induces CA3 dendritic atrophy in dorsal hippocampal neurons but does not alter learning and memory performance in adult offspring

Studies have demonstrated that nutrient deficiency during pregnancy or in early postnatal life results in structural abnormalities in the offspring hippocampus and in cognitive impairment. In an attempt to analyze whether gestational protein restriction might induce learning and memory impairments associated with structural changes in the hippocampus, we carried out a detailed morphometric analysis of the hippocampus of male adult rats together with the behavioral characterization of these animals in the Morris water maze (MWM). Our results demonstrate that gestational protein restriction leads to a decrease in total basal dendritic length and in the number of intersections of CA3 pyramidal neurons whereas the cytoarchitecture of CA1 and dentate gyrus remained unchanged. Despite presenting significant structural rearrangements, we did not observe impairments in the MWM test. Considering the clear dissociation between the behavioral profile and the hippocampus neuronal changes, the functional significance of dendritic remodeling in fetal processing remains undisclosed. © 2012 ISDN.