A simplified and higher dynamic range version of the J(1) ... J(4) method for optical phase measurements

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Interferometric measurements of nanometric displacements in a Piezoelectric Flextensional Actuator by using the new J1...J5 method

In this work, nanometric displacement amplitudes of a Piezoelectric Flextensional Actuator (PFA) designed using the topology optimization technique and operating in its linear range are measured by using a homodyne Michelson interferometer. A new improved version of the J1...J4 method for optical phase measurements, named J1...J5 method, is presented, which is of easier implementation than the original one. This is a passive phase detection scheme, unaffected by signal fading, source instabilities and changes in visibility. Experimental results using this improvement were compared with those obtained by using the J1... J4, J1...J6(pos) and J1...J 6(neg) methods, concluding that the dynamic range is increased while maintaining the sensitivity. Analysis based on the 1/f voltage noise and random fading show the new method is more stable to phase drift than all those methods. © 2012 IEEE.

The use of current transformers for noise detection due to sparking in insulators strings in high voltage transmission lines

In a general way, in an electric power utility the current transformers (CT) are used to measurement and protection of transmission lines (TL) 1 The Power Line Carriers systems (PLC) are used for communication between electrical substations and transmission line protection. However, with the increasing use of optical fiber to communication (due mainly to its high data transmission rate and low signal-noise relation) this application loses potentiality. Therefore, other functions must be defined to equipments that are still in using, one of them is detecting faults (short-circuits) and transmission lines insulator strings damages 2. The purpose of this paper is to verify the possibility of using the path to the ground offered by the CTs instead of capacitive couplings / capacitive potential transformers to detect damaged insulators, since the current transformers are always present in all transmission lines (TL's) bays. To this a comparison between this new proposal and the PLC previous proposed system 2 is shown, evaluating the economical and technical points of view. ©2010 IEEE.

Low voltage and variable-pressure scanning electron microscopy of fractured composites

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

A low-voltage wide-swing programmable-gain current amplifier

A CMOS low-voltage, wide-swing continuous-time current amplifier is presented. Exhibiting an open-loop architecture, the circuit is composed of transresistance and transconductance stages built upon triode-operating transistors. In addition to an extended dynamic range, the current gain can be programmed within good accuracy by a rapport involving only transistor geometries and tuning biases. Low temperature-drift on gain setting is then expected.In accordance with a 0.35 mum n-well CMOS fabrication process and a single 1.1 V-supply, a balanced current-amplifier is designed for a programmable gain-range of 6 - 34 dB and optimized with respect to dynamic range. Simulated results from PSPICE and Bsim3v3 models indicate, for a 100 muA(pp)-output current, a THD of 0.96 and 1.87% at 1 KHz and 100 KHz, respectively. Input noise is 120 pArootHz @ 10 Hz, with S/N = 63.2 dB @ 1%-THD. At maximum gain, total quiescent consumption is 334 muW. Measurements from a prototyped amplifier reveal a gain-interval of 4.8-33.1 dB and a maximum current swing of 120 muA(pp). The current-amplifier bandwidth is above 1 MHz.

Linear readout of dynamic phase modulation index in an optical voltage sensor using the new J(1) ... J(3) spectral method

The J(1)...J(3) is a recent optical method for linear readout of dynamic phase modulation index in homodyne interferometers. In this work, the J(1)... J(3) method is applied to measure voltage in an optical voltage sensor. Based on the classical J(1)...J(4) method, the J(1)... J(3) technique shows to be more stable to phase drift and simpler for implementation than the original one. The sensor dynamic range is enhanced. The agreement between theoretical and experimental results, based on 1/f noise, is demonstrated.

A linearly tunable low-voltage CMOS transconductor with improved common-mode stability and its application to (gm)-C filters

A linearly tunable low-voltage CMOS transconductor featuring a new adaptative-bias mechanism that considerably improves the stability of the processed-signal common,mode voltage over the tuning range, critical for very-low voltage applications, is introduced. It embeds a feedback loop that holds input devices on triode region while boosting the output resistance. Analysis of the integrator frequency response gives an insight into the location of secondary poles and zeros as function of design parameters. A third-order low-pass Cauer filter employing the proposed transconductor was designed and integrated on a 0.8-mum n-well CMOS standard process. For a 1.8-V supply, filter characterization revealed f(p) = 0.93 MHz, f(s) = 1.82 MHz, A(min) = 44.08, dB, and A(max) = 0.64 dB at nominal tuning. Mined by a de voltage V-TUNE, the filter bandwidth was linearly adjusted at a rate of 11.48 kHz/mV over nearly one frequency decade. A maximum 13-mV deviation on the common-mode voltage at the filter output was measured over the interval 25 mV less than or equal to V-TUNE less than or equal to 200 mV. For V-out = 300 mV(pp) and V-TUNE = 100 mV, THD was -55.4 dB. Noise spectral density was 0.84 muV/Hz(1/2) @1 kHz and S/N = 41 dB @ V-out = 300 mV(pp) and 1-MHz bandwidth. Idle power consumption was 1.73 mW @V-TUNE = 100 mV. A tradeoff between dynamic range, bandwidth, power consumption, and chip area has then been achieved.

On designing linearly-tunable ultra-low voltage CMOS gm-C filters

A linearly-tunable ULV transconductor featuring excellent stability of the processed signal common-mode voltage upon tuning, critical for very-low voltage applications, is presented. Its employment to the synthesis of CMOS gm-C high-frequency and voiceband filters is discussed. SPICE data describe the filter characteristics. For a 1.3 V-supply, their nominal passband frequencies are 1.0 MHz and 3.78 KHz, respectively, with tuning rates of 12.52 KHz/mV and 0.16 KHz/m V, input-referred noise spectral density of 1.3 μV/Hz1/2 and 5.0μV/Hz1/2 and standby consumption of 0.87 mW and 11.8 μW. Large-signal distortion given by THD = 1% corresponds to a differential output-swing of 360 mVpp and 480 mVpp, respectively. Common-mode voltage deviation is less than 4 mV over tuning interval.

A low-voltage programmable-gain current-mode amplifier

A CMOS low-voltage, wide-band continuous-time current amplifier is presented. Based on an open-loop topology, the circuit is composed by transresistance and transconductance stages built around triode-operating transistors. In addition to an extended dynamic range, the amplifier gain can be programmed within good accuracy by the rapport between the aspect-ratio of such transistors and tuning biases Vxand Vy. A balanced current-amplifier according to a single I. IV-supply and a 0.35μm fabrication process is designed. Simulated results from PSPiCE and Bsm3v3 models indicate a programmable gain within the range 20-34dB and a minimum break-frequency of IMHz @CL=IpF. For a 200 μApp-level, THD is 0.8% and 0.9% at IKHz and 100KHz, respectively. Input noise is 405pA√Hz @20dB-gain, which gives a SNR of 66dB @1MHz-bandwidth. Maximum quiescent power consumption is 56μ W. © 2002 IEEE.

A low-voltage low-sensitivity sinusoidal VCO for DPLL realizations

A quasi-sinusoidal linearly tunable OTA-C VCO built with triode-region transconductors is presented. Oscillation upon power-on is ensured by RHP poles associated with gate-drain capacitances of OTA input devices. Since the OTA nonlinearity stabilizes the amplitude, the oscillation frequency f0 is first-order independent of VDD, making the VCO adequate to mixed-mode designs. A range of simulations attests the theoretical analysis. As part of a DPLL, the VCO was prototyped on a 0.8μm CMOS process, occupying an area of 0.15mm2. Nominal f0 is 1MHz, with K VCo=8.4KHz/mV. Measured sensitivity to VDD is below 2.17, while phase noise is -86dBc at 100-KHz offset. The feasibility of the VCO for higher frequencies is verified by a redesign based on a 0.35μm CMOS process and VDD=3.3V, with a linear frequency-span of l3.2MHz - 61.5MHz.