A petri net based timing model for hardware/software co-design of digital systems

We have recently proposed an extension to Petri nets in order to be able to directly deal with all aspects of embedded digital systems. This extension is meant to be used as an internal model of our co-design environment. After analyzing relevant related work, and presenting a short introduction to our extension as a background material, we describe the details of the timing model we use in our approach, which is mainly based in Merlin's time model. We conclude the paper by discussing an example of its usage. © 2004 IEEE.

Automatic code generation for microcontrollers from place-transition Petri net models

This paper describes a program for the automatic generation of code for Intel's 8051 microcontroller. The code is generated from a place-transition Petri net specification. Our goal is to minimize programming time. The code generated by our program has been observed to exactly match the net model. It has also been observed that no change is needed to be made to the generated code for its compilation to the target architecture. © 2011 IFAC.

Finding best urban routes based on analyses of high level and IOPT Petri net models

This paper presents a tool that combines two kinds of Petri Net analyses to set the fastest routes to one vehicle in a bounded area of traffic urban. The first analysis consists of the discovery of possible routes in a state space generated from an IOPT Petri net model given the initial marking as the vehicle position. The second analysis receives the routes found in the first analysis and calculates the state equations at incidence matrix created from the High Level Petri net model to define the fastest route for each vehicle that arrive in the roads. It was considered the exchange of information between vehicle and infrastructure (V2I) to get the position and speed of all vehicles and support the analyses. With the results obtained we conclude that is possible optimizing the urban traffic flow if this tool is applied to all vehicles in a bounded urban traffic. © 2012 IEEE.

Controlling traffic jams on urban roads modeled in Coloured Petri net using Genetic Algorithm

This paper presents an application to traffic lights control in congested urban traffic, in real time, taking as input the position and route of the vehicles in the involved areas. This data is obtained from the communication between vehicles and infrastructure (V2I). Due to the great complexity of the possible combination of traffic lights and the short time to get a response, Genetic Algorithm was used to optimize this control. According to test results, the application can reduce the number of vehicles in congested areas, even with the entry of vehicles that previously were not being considered in these roads, such as parked vehicles. © 2012 IEEE.

Optimizing urban traffic flow using genetic algorithm with petri net analysis as fitness function

This paper describes a new methodology adopted for urban traffic stream optimization. By using Petri net analysis as fitness function of a Genetic Algorithm, an entire urban road network is controlled in real time. With the advent of new technologies that have been published, particularly focusing on communications among vehicles and roads infrastructures, we consider that vehicles can provide their positions and their destinations to a central server so that it is able to calculate the best route for one of them. Our tests concentrate on comparisons between the proposed approach and other algorithms that are currently used for the same purpose, being possible to conclude that our algorithm optimizes traffic in a relevant manner.

Arquitetura multiprocessada e reconfigurável para a síntese de redes de Petri em hardware

Uma arquitetura reconfigurável e multiprocessada para a implementação física de Redes de Petri foi desenvolvida em VHDL e mapeada sobre um FPGA. Convencionalmente, as Redes de Petri são transformadas em uma linguagem de descrição de hardware no nível de transferências entre registradores e um processo de síntese de alto nível é utilizado para gerar as funções booleanas e tabelas de transição de estado para que se possa, finalmente, mapeá-las num FPGA (Morris et al., 2000) (Soto and Pereira, 2001). A arquitetura proposta possui blocos lógicos reconfiguráveis desenvolvidos exclusivamente para a implementação dos lugares e das transições da rede, não sendo necessária a descrição da rede em níveis de abstração intermediários e nem a utilização de um processo de síntese para realizar o mapeamento da rede na arquitetura. A arquitetura permite o mapeamento de modelos de Redes de Petri com diferenciação entre as marcas e associação de tempo no disparo das transições, sendo composta por um arranjo de processadores reconfiguráveis, cada um dos quais representando o comportamento de uma transição da Rede de Petri a ser mapeada e por um sistema de comunicação, implementado por um conjunto de roteadores que são capazes de enviar pacotes de dados de um processador reconfigurável a outro. A arquitetura proposta foi validada num FPGA de 10.570 elementos lógicos com uma topologia que permitiu a implementação de Redes de Petri de até 9 transições e 36 lugares, atingindo uma latência de 15,4ns e uma vazão de até 17,12GB/s com uma freqüência de operação de 64,58MHz.

Petri nets and autonomous systems: A case study

This work presents the Petri net-based modeling of an autonomous robot's navigation system used for the application of supplies in agriculture. The model was developed theoretically and implemented through the CPNTools software. It simulates the behavior of the robot, capturing environmental characteristics by means of sensors, making appropriate decisions, and forwarding them to the corresponding actuators. By exciting the model using CPNTools it is possible to simulate situations that the robot might undergo, without the need to expose it to real potentially dangerous situations. ©2009 IEEE.

Digital system design process automation using place/transition petri nets

The constant increase in digital systems complexity definitely demands the automation of the corresponding synthesis process. This paper presents a computational environment designed to produce both software and hardware implementations of a system. The tool for code generation has been named ACG8051. As for the hardware synthesis there has been produced a larger environment consisting of four programs, namely: PIPE2TAB, AGPS, TABELA, and TAB2VHDL. ACG8051 and PIPE2TAB use place/transition net descriptions from PIPE as inputs. ACG8051 is aimed at generating assembly code for the 8051 micro-controller. PIPE2TAB produces a tabular version of a Mealy type finite state machine of the system, its output is fed into AGPS that is used for state allocation. The resulting digital system is then input to TABELA, which minimizes control functions and outputs of the digital system. Finally, the output generated by TABELA is fed to TAB2VHDL that produces a VHDL description of the system at the register transfer level. Thus, we present here a set of tools designed to take a high-level description of a digital system, represented by a place/transition net, and produces as output both an assembly code that can be immediately run on an 8051 micro-controller, and a VHDL description that can be used to directly implement the hardware parts either on an FPGA or as an ASIC.

Ferramentas para a integração de redes de Petri e VHDL na síntese de sistemas digitais

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Comparação de técnicas de redes de Petri na descrição de um pipeline

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Desenvolvimento de uma arquitetura multiprocessada e reconfigurável para a síntese de redes de Petri em hardware

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Geração automática de código para microcontroladores aplicada a um ambiente de co-projeto de hardware e software

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Petri nets teaching in the Mechatronics Engineering course

The current solutions implanted in the majority of manufacturing systems controlled by PLCs were developed through the language of programming known as ladder. Such a language, easily learned and handled, shows to be efficient whenever the system to be implanted does not demand greater complexity of analyses. Bigger systems, presenting characteristics in which resource compartments, parallelism and synchronizing among processes are more frequent, demand the adoption of solutions differentiation. This article presents a teaching experience and practical application of Petri nets in a Mechatronics Engineering graduation course. Copyright © 2007 IFAC.

Influence of stocking densities in the nursery phase on the growth of Macrobrachium amazonicum reared in net pens

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Ingestion rates of Artemia nauplii for different larval stages of Macrobrachium rosenbergii

The functional response between ingestion rate and food concentration was determined for each larval stage of Macrobrachium rosenbergii. Artemia franciscana nauplii were supplied at 2,4, 6, 8, 10 and 12 per milliliter. The nauplii were counted by sight using a Pasteur pipette and transferred to Petri dishes containing 40 ml of brackish water (12 parts per thousand) lying on the top of black plastic. One larva at each stage was individually placed into each Petri dish containing different food density. After 24 h, each larva was removed from the Petri dish and the leftover nauplii were counted. The amount consumed was determined by the difference between the initial and final number of nauplii. Ingestion rate (I) increased as food density (P) increased and was defined by the model I=I-m(1-e(-kP)). The results suggest four levels of ingestion during larval development. The first level includes stages II, III and IV, with average maximum consumption of about 40 nauplii/day; the second level includes stages V and VI, with consumption of approximately 55 nauplii/day; the third level includes stages VII and VIII, with consumption of 80-100 nauplii/day. The fourth level includes stages IX, X and XI, in which the high values for maximum ingestion (Im) exceed the load capacity of the medium. The low values for constant k (that may correspond to the adaptability of the food to prey characteristics, such as, size, mobility, etc.) obtained for stages IX, X and XI indicated that Artemia is not an adequate prey and there is necessity of a supplementary diet. The best relationship between predator and prey seemed to occur during stage IV Results obtained in the present work may subsidize future researches and serve as a guideline for practical considerations of feeding rates. (C) 2003 Elsevier B.V. B.V. All rights reserved.