Hardware implementation of type-2 programmable fuzzifier

The design of full programmable type-2 membership function circuit is presented in this paper. This circuit is used to implement the fuzzifier block of Type-2 Fuzzy Logic Controller chip. In this paper the type-2 fuzzy set was obtained by blurring the width of the type-1 fuzzy set. This circuit allows programming the height and the shape of the membership function. It operates in current mode, with supply voltage of 3.3V. The simulation results of interval type-2 membership function circuit have been done in CMOS 0.35μm technology using Mentor Graphics software. © 2011 IEEE.

The use of software Mapavox for teaching graphics and games to blind and low vision students: a development through practices

Current policies on education to visually impaired point for a growing trend of including students with special educational needs in regular schools. However, most often this inclusion is not accompanied by an appropriate professional trained or infrastructure, which has been presented as a big problem for regular school teachers who have students with visual impairments in their classroom. Based on this situation, the Group of Extension in Tactile Cartography from UNESP - University of the State of São Paulo - Campus de Rio Claro - SP - Brazil has been developing educational material of geography and cartography to blind students at a special school. Among the materials developed in this study highlight the development of graphics and board games provided with sound capabilities through MAPAVOX, software developed in partnership with UFRJ - Federal University from Rio de Janeiro - RJ - Brazil. Through this software, sound capabilities can be inserted into built materials, giving them a multi-sensory character. In most cases the necessary conditions for building specific materials to students with visual impairments is expensive and beyond the reach of features from a regular school, so the survey sought to use easy access and low cost materials like Cork, leaf aluminum, material for fixing and others. The development of these materials was supported by preparation in laboratory and its subsequent test through practices involving blind students. The methodology used on the survey is based on qualitative research and non comparative analysis of the results. In other words, the material is built based on the special students perception and reality construction, not being mere adaptations of visual materials, but a construction focused on the reality of the visually impaired. The results proved were quite successful as the materials prepared were effective on mediating the learning process of students with disabilities. Geographical and cartographic concepts were seized by the students through the technology used, associated with the use of materials that took into account in its building process the perception of the students.

Hardware implementation of an analog neural nonderivative optimizer

Analog neural systems that can automatically find the minimum value of the outputs of unknown analog systems, described by convex functions, are studied. When information about derivative or gradient are not used, these systems are called analog nonderivative optimizers. An electronic circuit for the analog neural nonderivative optimizer proposed by Teixeira and Zak, and its simulation with software PSPICE, is presented. With the simulation results and hardware implementation of the system, the validity of the proposed optimizer can be verified. These results are original, from the best of the authors knowledge.

Arquitetura multiprocessada e reconfigurável para a síntese de redes de Petri em hardware

Uma arquitetura reconfigurável e multiprocessada para a implementação física de Redes de Petri foi desenvolvida em VHDL e mapeada sobre um FPGA. Convencionalmente, as Redes de Petri são transformadas em uma linguagem de descrição de hardware no nível de transferências entre registradores e um processo de síntese de alto nível é utilizado para gerar as funções booleanas e tabelas de transição de estado para que se possa, finalmente, mapeá-las num FPGA (Morris et al., 2000) (Soto and Pereira, 2001). A arquitetura proposta possui blocos lógicos reconfiguráveis desenvolvidos exclusivamente para a implementação dos lugares e das transições da rede, não sendo necessária a descrição da rede em níveis de abstração intermediários e nem a utilização de um processo de síntese para realizar o mapeamento da rede na arquitetura. A arquitetura permite o mapeamento de modelos de Redes de Petri com diferenciação entre as marcas e associação de tempo no disparo das transições, sendo composta por um arranjo de processadores reconfiguráveis, cada um dos quais representando o comportamento de uma transição da Rede de Petri a ser mapeada e por um sistema de comunicação, implementado por um conjunto de roteadores que são capazes de enviar pacotes de dados de um processador reconfigurável a outro. A arquitetura proposta foi validada num FPGA de 10.570 elementos lógicos com uma topologia que permitiu a implementação de Redes de Petri de até 9 transições e 36 lugares, atingindo uma latência de 15,4ns e uma vazão de até 17,12GB/s com uma freqüência de operação de 64,58MHz.

Tensor3D: A computer graphics program to simulate 3D real-time deformation and visualization of geometric bodies

Tensor3D is a geometric modeling program with the capacity to simulate and visualize in real-time the deformation, specified through a tensor matrix and applied to triangulated models representing geological bodies. 3D visualization allows the study of deformational processes that are traditionally conducted in 2D, such as simple and pure shears. Besides geometric objects that are immediately available in the program window, the program can read other models from disk, thus being able to import objects created with different open-source or proprietary programs. A strain ellipsoid and a bounding box are simultaneously shown and instantly deformed with the main object. The principal axes of strain are visualized as well to provide graphical information about the orientation of the tensor's normal components. The deformed models can also be saved, retrieved later and deformed again, in order to study different steps of progressive strain, or to make this data available to other programs. The shape of stress ellipsoids and the corresponding Mohr circles defined by any stress tensor can also be represented. The application was written using the Visualization ToolKit, a powerful scientific visualization library in the public domain. This development choice, allied to the use of the Tcl/Tk programming language, which is independent on the host computational platform, makes the program a useful tool for the study of geometric deformations directly in three dimensions in teaching as well as research activities. (C) 2007 Elsevier Ltd. All rights reserved.

Evolvable hardware applied to voice recognition

This paper presents some results of the application on Evolvable Hardware (EHW) in the area of voice recognition. Evolvable Hardware is able to change inner connections, using genetic learning techniques, adapting its own functionality to external condition changing. This technique became feasible by the improvement of the Programmable Logic Devices. Nowadays, it is possible to have, in a single device, the ability to change, on-line and in real-time, part of its own circuit. This work proposes a reconfigurable architecture of a system that is able to receive voice commands to execute special tasks as, to help handicapped persons in their daily home routines. The idea is to collect several voice samples, process them through algorithms based on Mel - Ceptrais theory to obtain their numerical coefficients for each sample, which, compose the universe of search used by genetic algorithm. The voice patterns considered, are limited to seven sustained Portuguese vowel phonemes (a, eh, e, i, oh, o, u).

A petri net based timing model for hardware/software co-design of digital systems

We have recently proposed an extension to Petri nets in order to be able to directly deal with all aspects of embedded digital systems. This extension is meant to be used as an internal model of our co-design environment. After analyzing relevant related work, and presenting a short introduction to our extension as a background material, we describe the details of the timing model we use in our approach, which is mainly based in Merlin's time model. We conclude the paper by discussing an example of its usage. © 2004 IEEE.

Integrating interaction resources in the graphics clusters

This paper aims to describe the basic concepts and necessary for Java programs can invoke libraries of programming language C/C ++, through the JNA API. We used a library developed in C/C ++ called Glass [8], which offers a solution for viewing 3D graphics, using graphics clusters, reducing the cost of viewing. The purpose of the work is to interact with the humanoid developed using Java, which makes movements of LIBRAS language for the deaf, as Glass's, so that through this they can view the information using stereoscopic multi-view in full size. ©2010 IEEE.

Desenvolvimento de hardware e software para tratamento e visualização de dados de descargas atmosféricas aplicados à segurança da navegação hidroviária

Pós-graduação em Engenharia Elétrica - FEIS

Geração automática de código para microcontroladores aplicada a um ambiente de co-projeto de hardware e software

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Monitoramento da queima da peça no processo de retificação plana baseado no estudo espectral do sinal de emissão acústica com implementação por hardware

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Implementação em hardware de um sistema inteligente para detecção de plantas daninhas em plantações de soja utilizando máquinas de vetores de suporte e redes neurais artificiais

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

FLEXLAB: Middleware de virtualização de hardware para gerenciamento centralizado de computadores em rede

Pós-graduação em Ciência da Computação - IBILCE

Implementação de uma plataforma HW/SW para automação industrial, utilizando hardware reconfigurável com processador NIOS II em conformidade com o padrão IEEE 1451

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Desenvolvimento de uma arquitetura multiprocessada e reconfigurável para a síntese de redes de Petri em hardware

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)