Separating interface state response from parasitic effects in conductance measurements on organic metal-insulator-semiconductor capacitors

A simple model is developed for the admittance of a metal-insulator-semiconductor (MIS) capacitor which includes the effect of a guard ring surrounding the Ohmic contact to the semiconductor. The model predicts most of the features observed in a MIS capacitor fabricated using regioregular poly(3-hexylthiophene) as the active semiconductor and polysilsesquioxane as the gate insulator. In particular, it shows that when the capacitor is driven into accumulation, the parasitic transistor formed by the guard ring and Ohmic contact can give rise to an additional feature in the admittance-voltage plot that could be mistaken for interface states. When this artifact and underlying losses in the bulk semiconductor are accounted for, the remaining experimental feature, a peak in the loss-voltage plot when the capacitor is in depletion, is identified as an interface (or near interface) state of density of similar to 4 x 10(10) cm(-2) eV(-1). Application of the model shows that exposure of a vacuum-annealed device to laboratory air produces a rapid change in the doping density in the channel region of the parasitic transistor but only slow changes in the bulk semiconductor covered by the gold Ohmic contact. (C) 2008 American Institute of Physics.

Thermal dependence of the zero-bias conductance through a nanostructure

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Universal zero-bias conductance through a quantum wire side-coupled to a quantum dot

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Universal zero-bias conductance for the single-electron transistor

The thermal dependence of the zero-bias conductance for the single electron transistor is the target of two independent renormalization-group approaches, both based on the spin-degenerate Anderson impurity model. The first approach, an analytical derivation, maps the Kondo-regime conductance onto the universal conductance function for the particle-hole symmetric model. Linear, the mapping is parametrized by the Kondo temperature and the charge in the Kondo cloud. The second approach, a numerical renormalization-group computation of the conductance as a function the temperature and applied gate voltages offers a comprehensive view of zero-bias charge transport through the device. The first approach is exact in the Kondo regime; the second, essentially exact throughout the parametric space of the model. For illustrative purposes, conductance curves resulting from the two approaches are compared.

Temporal dynamics of stomatal conductance of plants under water deficit: can homeostasis be improved by more complex dynamics?

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Universal conductance for the Anderson model

We discuss the thermal dependence of the zero-bias electrical conductance for a quantum dot embedded in a quantum wire, or side-coupled to it. In the Kondo regime, the temperature-dependent conductances map linearly onto the conductance for the symmetric Anderson Hamiltonian. The mapping fits accurately numerical renormalization-group results for the conductance in each geometry. In the side-coupled geometry, the conductance is markedly affected by a gate potential applied to the wire; in the embedded geometry, it is not. © 2010 IOP Publishing Ltd.