Sintetizador analógico de sinais ortogonais: projeto e construção usando tecnologia CMOS

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Arrays of gold microelectrodes made from split integrated circuit chips

A simple and inexpensive way to fabricate arrays of gold microelectrodes is proposed. Integrated circuit chips are sawed through their middle, normal to the longest axis, leading to destruction of the silicon circuit and rupture of the gold wires that interconnect it with the external terminals. Polishing the resulting rough surface converts the tips of the wires embedded in the chip halves into arrays of gold microdisks of about 25 mu m diameter. The number of active microelectrodes (MEs), of an array depends on the number of pins in the chip, n, being typically (n/2)-4. These MEs can be used individually or externally interconnected in any combination. X-ray images of the chips and micrographs of the resulting surface of the polished arrays have revealed variable distances between neighbor MEs, which are, however, larger than 10 times the radius of the disks. This feature of the MEs prevents diffusional cross-talk between electrodes. The use of these microdisk electrodes for analytical purposes exhibits sigmoidal voltammograms, and chronoamperometric experiments confirm the nonlinear i vs. t(1/2) plots, typical for processes where radial diffusion prevails. Satisfactory uniformity was observed for the response of each electrode of an array, indicating similarity of geometry and disk areas. The potentialities of these MEs were demonstrated by the determination of cadmium at ppb levels using square wave voltammetry with preconcentration. Due to the relative ease with which these MEs can be manufactured and their good performance in (chemical) analysis, wide applications in electrochemistry and electroanalysis is envisioned.

Flow-through cell based on an array of gold microelectrodes obtained from modified integrated circuit chips

The construction of a flow-through cell incorporating an array of gold microelectrodes is described and its application to flow injection analysis with amperometric detection is presented, Simple modification of almost any conventional integrated circuit chip, used as an inexpensive source of pre-assembled gold micro-wires, leads to the rapid and successful preparation of arrays of 8-48 elements, the polymeric encapsulation material from the top face of the chip is removed by abrasion until the gold micro-mires (used to interconnect the silicon circuit to the external contact pins of the chip) are disrupted and their transversal (elliptical) sections become exposed. Once polished, the flat and smooth top surface of the gold microelectrode-array chip (MEAC) is provided with a spacer and fitted under pressure against an acrylic block with the reference and auxiliary electrodes, to form the electrochemical (thin-layer) flow cell, while the contact pins are plugged into a standard IC socket, This design ensures autonomous electric contact with each electrode and allows fast dismantling for polishing or substitution, the performance of flow cells with MEACs was investigated utilizing the technique of reverse pulse amperometry without oxygen removal, A method was established for the determination of the copper concentration in sugar cane spirit, regulated by law for beverages, Samples from industrial producers and small-scale (alembic) brewers were compared, With a 24 MEAC, a detection limit of 30 mu g I-l of copper (4.7 x 10(-7) mol l(-1) of Cu-II for 100 mu l injections) was calculated, Routine operation was established at a frequency of 60-90 determinations per hour, Intercomparison with atomic absorption spectrometric determinations resulted in excellent agreement.

A multisampling time-domain CMOS imager with synchronous readout circuit

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

An analog implementation of radial basis neural networks (RBNN) using BiCMOS technology

This paper describes a analog implementation of radial basis neural networks (RBNN) in BiCMOS technology. The RBNN uses a gaussian function obtained through the characteristic of the bipolar differential pair. The gaussian parameters (gain, center and width) is changed with programmable current source. Results obtained with PSPICE software is showed.

Desenvolvimento de um sintetizador de freqüência de baixo custo em tecnologia CMOS

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Low voltage four-quadrant current multiplier: an improved topology for n-well CMOS process

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

A low-voltage wide-swing programmable-gain current amplifier

A CMOS low-voltage, wide-swing continuous-time current amplifier is presented. Exhibiting an open-loop architecture, the circuit is composed of transresistance and transconductance stages built upon triode-operating transistors. In addition to an extended dynamic range, the current gain can be programmed within good accuracy by a rapport involving only transistor geometries and tuning biases. Low temperature-drift on gain setting is then expected.In accordance with a 0.35 mum n-well CMOS fabrication process and a single 1.1 V-supply, a balanced current-amplifier is designed for a programmable gain-range of 6 - 34 dB and optimized with respect to dynamic range. Simulated results from PSPICE and Bsim3v3 models indicate, for a 100 muA(pp)-output current, a THD of 0.96 and 1.87% at 1 KHz and 100 KHz, respectively. Input noise is 120 pArootHz @ 10 Hz, with S/N = 63.2 dB @ 1%-THD. At maximum gain, total quiescent consumption is 334 muW. Measurements from a prototyped amplifier reveal a gain-interval of 4.8-33.1 dB and a maximum current swing of 120 muA(pp). The current-amplifier bandwidth is above 1 MHz.

On designing linearly-tunable ultra-low voltage CMOS gm-C filters

A linearly-tunable ULV transconductor featuring excellent stability of the processed signal common-mode voltage upon tuning, critical for very-low voltage applications, is presented. Its employment to the synthesis of CMOS gm-C high-frequency and voiceband filters is discussed. SPICE data describe the filter characteristics. For a 1.3 V-supply, their nominal passband frequencies are 1.0 MHz and 3.78 KHz, respectively, with tuning rates of 12.52 KHz/mV and 0.16 KHz/m V, input-referred noise spectral density of 1.3 μV/Hz1/2 and 5.0μV/Hz1/2 and standby consumption of 0.87 mW and 11.8 μW. Large-signal distortion given by THD = 1% corresponds to a differential output-swing of 360 mVpp and 480 mVpp, respectively. Common-mode voltage deviation is less than 4 mV over tuning interval.

Design of a CMOS voltage reference using current-model approach

A voltage reference with low sensibility to temperature and power-supply that can generate flexible reference values (from milivolts to several volts) is proposed. Designed for AMS 0.35μm CMOS process, the circuit provides a stable output voltage working in the temperature range of -40-150°C. The proposed reference provides a nominal output voltage of 1.358V with a power-supply of 3.3V. © 2011 IEEE.

Methodology analysis of a computational tool used in electronic circuit design

This paper considers the importance of using a top-down methodology and suitable CAD tools in the development of electronic circuits. The paper presents an evaluation of the methodology used in a computational tool created to support the synthesis of digital to analog converter models by translating between different tools used in a wide variety of applications. This tool is named MS 2SV and works directly with the following two commercial tools: MATLAB/Simulink and SystemVision. Model translation of an electronic circuit is achieved by translating a mixed-signal block diagram developed in Simulink into a lower level of abstraction in VHDL-AMS and the simulation project support structure in SystemVision. The method validation was performed by analyzing the power spectral of the signal obtained by the discrete Fourier transform of a digital to analog converter simulation model. © 2011 IEEE.

An analog implementation of radial basis function network appropriate for transducer linearizer

A circuit for transducer linearizer tasks have been designed and built using discrete components and it implements by: a Radial Basis Function Network (RBFN) with three basis functions. The application in a linearized thermistor showed that the network has good approximation capabilities. The circuit advantages is the amplitude, width and center.

A current-mode based Field-Programmable Analog Array for signal processing applications

This paper presents a new approach to develop Field Programmable Analog Arrays (FPAAs),(1) which avoids excessive number of programming elements in the signal path, thus enhancing the performance. The paper also introduces a novel FPAA architecture, devoid of the conventional switching and connection modules. The proposed FPAA is based on simple current mode sub-circuits. An uncompounded methodology has been employed for the programming of the Configurable Analog Cell (CAC). Current mode approach has enabled the operation of the FPAA presented here, over almost three decades of frequency range. We have demonstrated the feasibility of the FPAA by implementing some signal processing functions.

A linearly-tunable OTA-C sinusoidal oscillator for low-voltage applications

A low-voltage, low-power OTA-C sinusoidal oscillator based on a triode-MOSFET transconductor is here discussed. The classical quadrature model is employed and the transconductor inherent nonlinear characteristic with input voltage is used as the amplitude-stabilization element. An external bias VTUNE linearly adjusts the oscillation frequency. According to a standard 0.8μm CMOS n-well process, a prototype was integrated, with an effective area of 0.28mm2. Experimental data validate the theoretical analysis. For a single 1.8V-supply and 100mV≤VTUNE≤250mV, the oscillation frequency fo ranges from 0.50MHz to 1.125MHz, with a nearly constant gain KVCO=4.16KHz/mV. Maximum output amplitude is 374mVpp @1.12MHz. THD is -41dB @321mVpp. Maximum average consumption is 355μW.

On designing linearly tunable high-Q OTA-C filters with low sensitivity

This paper discusses a design approach for a high-Q low-sensitivity OTA-C biquad bandpass section. An optimal relationship is established between transconductances defining the differenceβ - γ in the Q-factor denominator, setting the Q-sensitivity to tuning voltages around unity. A 30-MHz filter was designed based on a 0.35μn CMOS process and VDD=3.3V. A range of circuit simulation supports the theoretical analysis. Q-factor spans from 20.5 to 60, while ensuring filter stability along the tuning range. Although a Mode-operating OTA is used, the procedure can be extended to other types of transconductor.