Um estudo sobre a apreciação do raciocínio matemático na formação inicial de professores

The present work focused on developing teaching activities that would provide to the student in initial teacher training, improving the ability of mathematical reasoning and hence a greater appreciation of the concepts related to the golden section, the irrational numbers, and the incommensurability the demonstration from the reduction to the nonsensical. This survey is classified itself as a field one which data collection were inserted within a quantitative and qualitative approach. Acted in this research, two classes in initial teacher training. These were teachers and employees of public schools and local governments, living in the capital, in Natal Metropolitan Region - and within the country. The empirical part of the research took place in Pedagogy and Mathematics courses, IFESP in Natal - RN. The theoretical and methodological way construction aimed to present a teaching situation, based on history, involving mathematics and architecture, derived from a concrete context - Andrea Palladio s Villa Emo. Focused discussions on current studies of Rachel Fletcher stating that the architect used the golden section in this village construction. As a result, it was observed that the proposal to conduct a study on the mathematical reasoning assessment provided, in teaching and activity sequences, several theoretical and practical reflections. These applications, together with four sessions of study in the classroom, turned on to a mathematical thinking organization capable to develop in academic students, the investigative and logical reasoning and mathematical proof. By bringing ancient Greece and Andrea Palladio s aspects of the mathematics, in teaching activities for teachers and future teachers of basic education, it was promoted on them, an improvement in mathematical reasoning ability. Therefore, this work came from concerns as opportunity to the surveyed students, thinking mathematically. In fact, one of the most famous irrational, the golden section, was defined by a certain geometric construction, which is reflected by the Greek phrase (the name "golden section" becomes quite later) used to describe the same: division of a segment - on average and extreme right. Later, the golden section was once considered a standard of beauty in the arts. This is reflected in how to treat the statement questioning by current Palladio s scholars, regarding the use of the golden section in their architectural designs, in our case, in Villa Emo

Contribuição para o estudo do embarque de uma rede neural artificial em field programmable gate array (FPGA)

This study shows the implementation and the embedding of an Artificial Neural Network (ANN) in hardware, or in a programmable device, as a field programmable gate array (FPGA). This work allowed the exploration of different implementations, described in VHDL, of multilayer perceptrons ANN. Due to the parallelism inherent to ANNs, there are disadvantages in software implementations due to the sequential nature of the Von Neumann architectures. As an alternative to this problem, there is a hardware implementation that allows to exploit all the parallelism implicit in this model. Currently, there is an increase in use of FPGAs as a platform to implement neural networks in hardware, exploiting the high processing power, low cost, ease of programming and ability to reconfigure the circuit, allowing the network to adapt to different applications. Given this context, the aim is to develop arrays of neural networks in hardware, a flexible architecture, in which it is possible to add or remove neurons, and mainly, modify the network topology, in order to enable a modular network of fixed-point arithmetic in a FPGA. Five synthesis of VHDL descriptions were produced: two for the neuron with one or two entrances, and three different architectures of ANN. The descriptions of the used architectures became very modular, easily allowing the increase or decrease of the number of neurons. As a result, some complete neural networks were implemented in FPGA, in fixed-point arithmetic, with a high-capacity parallel processing