3 resultados para planarization
em Deakin Research Online - Australia
Resumo:
Chemical mechanical polishing technique is more frequently adopted for planarization in integrated circuit fabrication. The silica abrasives in colloidal state are fabricated with the sodium silicate solution as raw materials through the polymerization reaction among silicic acid molecules. By continuous injection of silicic acid into the preexisting silica solution, the diameter of silica nanoparticles increases. The different sized silica nanoparticles are imaged by scanning electron microscopy, and the dried silica are characterized by X-ray diffraction and thermal analysis. The polishing test on silicon wafer with as-fabricated silica abrasives shows that the surface flatness reaches 1.1 nm roughness, however, micro scratches are still present in the surface.
Resumo:
This paper presents an optimized fabrication method for developing a freestanding bridge for RF MEMS switches. In this method, the sacrificial layer is patterned and hard baked a 220°C for 3min, after filling the gap between the slots of the coplanar waveguide. Measurement results by AFM and SEM demonstrate that this technique significantly improves the planarity of the sacrificial layer, reducing the uneven surface to less than 20nm, and the homogeneity of the Aluminum thickness across the bridge. Moreover, a mixture of O2, Ar and CF4 was used and optimized for dry releasing of the bridge. A large membrane (200×100μm2) was released without any surface bending. Therefore, this method not only simplifies the fabrication process, but also improves the surface flatness and edge smoothness of the bridge. This fabrication method is fully compatible with standard silicon IC technology.