A double data rate (DDR) architecture for OFDM based wireless consumer devices

The creation of OFDM based Wireless Personal Area Networks (WPANs) has allowed the development of high bit-rate wireless communication devices suitable for streaming High Definition video between consumer products, as demonstrated in Wireless-USB and Wireless-HDMI. However, these devices need high frequency clock rates, particularly for the OFDM, FFT and symbol processing sections resulting in high silicon cost and high electrical power. The high clock rates make hardware prototyping difficult and verification is therefore very important but costly. Acknowledging that electrical power in wireless consumer devices is more critical than the number of implemented logic gates, this paper presents a Double Data Rate (DDR) architecture for implementation inside a OFDM baseband codec in order to reduce the high frequency clock rates by a complete factor of 2. The presented architecture has been implemented and tested for ECMA-368 (Wireless- USB context) resulting in a maximum clock rate of 264MHz instead of the expected 528MHz clock rate existing anywhere on the baseband codec die.

Dual carrier modulation soft demapper

An Orthogonal Frequency Division Multiplexing (OFDM) communication system with a transmitter and a receiver. The transmitter is arranged to transmit channel estimation sequences on each of a plurality of band groups, or bands, and to transmit data on each of the band groups or bands. The receiver is arranged to receive the channel estimation sequences for each band group or band to calculate channel state information from each of the channel estimation sequences transmitted on that band group or band and to form an average channel state information. The receiver receives the transmitted data, transforms the received data into the frequency domain, equalizes the received data using the channel state information, demaps the equalized data to re-construct the received data as soft bits and modifies the soft bits using the averaged channel state information.

A double data rate (DDR) architecture for OFDM based wireless consumer devices

The creation of OFDM based Wireless Personal Area Networks (WPANs) has allowed high bit-rate wireless communication devices suitable for streaming High Definition video between consumer products as demonstrated in Wireless- USB. However, these devices need high clock rates, particularly for the OFDM sections resulting in high silicon cost and high electrical power. Acknowledging that electrical power in wireless consumer devices is more critical than the number of implemented logic gates, this paper presents a Double Data Rate (DDR) architecture to reduce the OFDM input and output clock rate by a factor of 2. The architecture has been implemented and tested for Wireless-USB (ECMA-368) resulting in a maximum clock of 264MHz instead of 528MHz existing anywhere on the die.

Inhibition of cellular proliferation by the genistein metabolite 5,7,3',4'-tetrahydroxyisoflavone is mediated by DNA damage and activation of the ATR signalling pathway

The cellular actions of genistein, and its in vivo metabolites, are believed to mediate the decreased risk of breast cancer associated with high soy consumption. The genistein metabolite, 5,7,3',4'-tetrahydroxyisoflavone (THIF), induced G2-M cell cycle arrest in T47D tumorigenic breast epithelial cells via a mechanism involving the activation of ataxia telangiectasia and Rad3-related kinase (ATR) via its phosphorylation at Ser(428). This activation of ATR appeared to result from THIF-induced increases in intracellular oxidative stress, a depletion of cellular GSH and an increase in DNA strand breakage. THIF treatment also led to an inhibition of cdc2, which was accompanied by the phosphorylation of both p53 (Ser(15)) and Chk1 (Ser(296)) and the de-activation of cdc25C phosphatase. We suggest the anti-proliferative actions of THIF may be mediated by initial oxidative DNA damage, activation of ATR and downstream regulation of the p53 and Chk1 pathways leading to cell cycle arrest in G2-M. This may represent one mechanism by which genistein exerts its cellular activity in vivo. (c) 2007 Elsevier Inc. All rights reserved.

(-)Epicatechin stimulates ERK-dependent cyclic AMP response element activity and up-regulates GluR2 in cortical neurons

Emerging evidence suggests that the cellular actions of flavonoids relate not simply to their antioxidant potential but also to the modulation of protein kinase signalling pathways. We investigated in primary cortical neurons, the ability of the flavan-3-ol, (-)epicatechin, and its human metabolites at physiologically relevant concentrations, to stimulate phosphorylation of the transcription factor cAMP-response element binding protein (CREB), a regulator of neuronal viability and synaptic plasticity. (-)Epicatechin at 100-300 nmol/L stimulated a rapid, extracellular signal-regulated kinase (ERK)- and PI3K-dependent, increase in CREB phosphorylation. At micromolar concentrations, stimulation was no longer apparent and at the highest concentration tested (30 mu mol/L) (-)epicatechin was inhibitory. (-)Epicatechin also stimulated ERK and Akt phosphorylation with similar bell-shaped concentration-response characteristics. The human metabolite 3 '-O-methyl-(-)epicatechin was as effective as (-)epicatechin at stimulating ERK phosphorylation, but (-)epicatechin glucuronide was inactive. (-)Epicatechin and 3 '-O-methyl-(-)epicatechin treatments (100 nmol/L) increased CRE-luciferase activity in cortical neurons in a partially ERK-dependent manner, suggesting the potential to increase CREB-mediated gene expression. mRNA levels of the glutamate receptor subunit GluR2 increased by 60%, measured 18 h after a 15 min exposure to (-)epicatechin and this translated into an increase in GluR2 protein. Thus, (-)epicatechin has the potential to increase CREB-regulated gene expression and increase GluR2 levels and thus modulate neurotransmission, plasticity and synaptogenesis.

The intracellular genistein metabolite 5,7,3 ',4 '-tetrahydroxyisoflavone mediates G2-M cell cycle arrest in cancer cells via modulation of the p38 signaling pathway

The cellular actions of genistein are believed to mediate the decreased risk of breast cancer associated with high soy consumption. We have investigated the intracellular metabolism of genistein in T47D tumorigenic and MCF-10A nontumorigenic cells and assessed the cellular actions of resultant metabolites. Genistein selectively induced growth arrest and G2-M phase cell cycle block in T47D but not MCF10A breast epithelial cells. These antiproliferative effects were paralleled by significant differences in the association of genistein to cells and in particular its intracellular metabolism. Genistein was selectively taken up into T47D cells and was subject to metabolism by CYP450 enzymes leading to the formation of both 5,7,3',4'-tetrahydroxyisoflavone (THIF) and two glutathionyl conjugates of THIF THIF inhibited cdc2 activation via the phosphorylation of p38 MAP kinase, suggesting that this species may mediate genistein's cellular actions. THIF exposure activated p38 and caused subsequent inhibition of cyclin B1 (Ser 147) and cdc2 (Thr 161) phosphorylation, two events critical for the correct functioning of the cdc2-cyclin B1 complex. We suggest that the formation of THIF may mediate the cellular actions of genistein in tumorigenic breast epithelial cells via the activation of signaling through p38. (c) 2006 Elsevier Inc. All rights reserved.

Investigation into low power of a 2D Inverse Discrete CosineTransform (IDCT) in FPGAs

Design for low power in FPGA is rather limited since technology factors affecting power are either fixed or limited for FPGA families. This paper investigates opportunities for power savings of a pipelined 2D IDCT design at the architecture and logic level. We report power consumption savings of over 25% achieved in FPGA circuits obtained from clock gating implementation of optimizations made at the algorithmic level(1).

Pullpipelining: A technique for systolic pipelined circuits

Pullpipelining, a pipeline technique where data is pulled from successor stages from predecessor stages is proposed Control circuits using a synchronous, a semi-synchronous and an asynchronous approach are given. Simulation examples for a DLX generic RISC datapath show that common control pipeline circuit overhead is avoided using the proposal. Applications to linear systolic arrays in cases when computation is finished at early stages in the array are foreseen. This would allow run-time data-driven digital frequency modulation of synchronous pipelined designs. This has applications to implement algorithms exhibiting average-case processing time using a synchronous approach.

Power performance with gated clocks of a pipelined Cordic Core

This paper presents the evaluation in power consumption of gated clocks pipelined circuits with different register configurations in Virtex-based FPGA devices. Power impact of a gated clock circuitry aimed at reducing flip-flops output rate at the bit level is studied. Power performance is also given for pipeline stages based on the implementation of a double edge-triggered flip-flop. Using a pipelined Cordic Core circuit as an example, this study did not find evidence in power benefits either when gated clock at the bit-level or double-edge triggered flip-flops used when synthesized with FPGA logic resources.

Verification and FPGA circuits of a block-2 fast path-based predictor

This paper formally derives a new path-based neural branch prediction algorithm (FPP) into blocks of size two for a lower hardware solution while maintaining similar input-output characteristic to the algorithm. The blocked solution, here referred to as B2P algorithm, is obtained using graph theory and retiming methods. Verification approaches were exercised to show that prediction performances obtained from the FPP and B2P algorithms differ within one mis-prediction per thousand instructions using a known framework for branch prediction evaluation. For a chosen FPGA device, circuits generated from the B2P algorithm showed average area savings of over 25% against circuits for the FPP algorithm with similar time performances thus making the proposed blocked predictor superior from a practical viewpoint.

A new organization for a perceptron-based branch predictor and its FPGA implementation

An unaltered rearrangement of the original computation of a neural based predictor at the algorithmic level is introduced as a new organization. Its FPGA implementation generates circuits that are 1.7 faster than a direct implementation of the original algorithm. This faster clock rate allows to implement predictors with longer history lengths using the nearly the same hardware budget.

FPGA organization for the fast path-based neural branch predictor

This paper develops cycle-level FPGA circuits of an organization for a fast path-based neural branch predictor Our results suggest that practical sizes of prediction tables are limited to around 32 KB to 64 KB in current FPGA technology due mainly to FPGA area of logic resources to maintain the tables. However the predictor scales well in terms of prediction speed. Table sizes alone should not be used as the only metric for hardware budget when comparing neural-based predictor to predictors of totally different organizations. This paper also gives early evidence to shift the attention on to the recovery from mis-prediction latency rather than on prediction latency as the most critical factor impacting accuracy of predictions for this class of branch predictors.

Fractal quantization

A Fractal Quantizer is proposed that replaces the expensive division operation for the computation of scalar quantization by more modest and available multiplication, addition and shift operations. Although the proposed method is iterative in nature, simulations prove a virtually undetectable distortion to the naked eve for JPEG compressed images using a single iteration. The method requires a change to the usual tables used in JPEG algorithins but of similar size. For practical purposes, performing quantization is reduced to a multiplication plus addition operation easily programmed in either low-end embedded processors and suitable for efficient and very high speed implementation in ASIC or FPGA hardware. FPGA hardware implementation shows up to x15 area-time savingscompared to standars solutions for devices with dedicated multipliers. The method can be also immediately extended to perform adaptive quantization(1).

Experiences applying OVM 2.0 to an 8B/10B RTL design

The SystemVerilog implementation of the Open Verification Methodology (OVM) is exercised on an 8b/10b RTL open core design in the hope of being a simple yet complete exercise to expose the key features of OVM. Emphasis is put onto the actual usage of the verification components rather than a complete verification flow aiming at being of help to readers unfamiliar with OVM seeking to apply the methodology to their own designs. A link that takes you to the complete code is given to reinforce this aim. We found the methodology easy to use but intimidating at first glance specially for someone with little experience in object oriented programming. However it is clear to see the flexibility, portability and reusability of verification code once you manage to give some first steps.

An efficient low power FFT implementation for multiband full-rate ultra-wideband (UWB) receivers

This paper discusses the design, implementation and synthesis of an FFT module that has been specifically optimized for use in the OFDM based Multiband UWB system, although the work is generally applicable to many other OFDM based receiver systems. Previous work has detailed the requirements for the receiver FFT module within the Multiband UWB ODFM based system and this paper draws on those requirements coupled with modern digital architecture principles and low power design criteria to converge on our optimized solution. The FFT design obtained in this paper is also applicable for implementation of the transmitter IFFT module therefore only needing one FFT module for half-duplex operation. The results from this paper enable the baseband designers of the 200Mbit/sec variant of Multiband UWB systems (and indeed other OFDM based receivers) using System-on-Chip (SoC), FPGA and ASIC technology to create cost effective and low power solutions biased toward the competitive consumer electronics market.