Correlating Bayesian date estimates with climatic events and domestication using a bovine case study

The tribe Bovini contains a number of commercially and culturally important species, such as cattle. Understanding their evolutionary time scale is important for distinguishing between post-glacial and domestication-associated population expansions, but estimates of bovine divergence times have been hindered by a lack of reliable calibration points. We present a Bayesian phylogenetic analysis of 481 mitochondrial D-loop sequences, including 228 radiocarbon-dated ancient DNA sequences, using a multi-demographic coalescent model. By employing the radiocarbon dates as internal calibrations, we co-estimate the bovine phylogeny and divergence times in a relaxed-clock framework. The analysis yields evidence for significant population expansions in both taurine and zebu cattle, European aurochs and yak clades. The divergence age estimates support domestication-associated expansion times (less than 12 kyr) for the major haplogroups of cattle. We compare the molecular and palaeontological estimates for the Bison-Bos divergence.

A double data rate (DDR) architecture for OFDM based wireless consumer devices

The creation of OFDM based Wireless Personal Area Networks (WPANs) has allowed the development of high bit-rate wireless communication devices suitable for streaming High Definition video between consumer products, as demonstrated in Wireless-USB and Wireless-HDMI. However, these devices need high frequency clock rates, particularly for the OFDM, FFT and symbol processing sections resulting in high silicon cost and high electrical power. The high clock rates make hardware prototyping difficult and verification is therefore very important but costly. Acknowledging that electrical power in wireless consumer devices is more critical than the number of implemented logic gates, this paper presents a Double Data Rate (DDR) architecture for implementation inside a OFDM baseband codec in order to reduce the high frequency clock rates by a complete factor of 2. The presented architecture has been implemented and tested for ECMA-368 (Wireless- USB context) resulting in a maximum clock rate of 264MHz instead of the expected 528MHz clock rate existing anywhere on the baseband codec die.

A double data rate (DDR) architecture for OFDM based wireless consumer devices

The creation of OFDM based Wireless Personal Area Networks (WPANs) has allowed high bit-rate wireless communication devices suitable for streaming High Definition video between consumer products as demonstrated in Wireless- USB. However, these devices need high clock rates, particularly for the OFDM sections resulting in high silicon cost and high electrical power. Acknowledging that electrical power in wireless consumer devices is more critical than the number of implemented logic gates, this paper presents a Double Data Rate (DDR) architecture to reduce the OFDM input and output clock rate by a factor of 2. The architecture has been implemented and tested for Wireless-USB (ECMA-368) resulting in a maximum clock of 264MHz instead of 528MHz existing anywhere on the die.

Environmental control for layers

Light patterns have less effect on numbers of eggs laid by current stocks than on those of forty years ago, but the principles have not changed. Ovarian activity is stimulated by increasing photoperiods and suppressed by decreasing photoperiods. The light pattern used during rearing can still have large effects on age at 50% lay, even for modern stocks. Early sexual maturity maximises egg numbers but gives smaller eggs. Late maturity maximises egg size at the expense of numbers. The relationship between egg output (g/hen d) and age at first egg is curvilinear, with maximum yield occurring in flocks maturing in about the centre of their potential range. Fancy patterns of increasing daylength after maturity are probably not justified. A flock held on a constant 14h day will lay as many eggs as one given step up lighting. Intermittent lighting saves about 5% of feed consumption with no loss of output, provided that the feed has adequate amino acid content to allow for the reduced feed intake. Producers with light-proof laying houses should be taking advantage of intermittent lighting. The recommended light intensity for laying houses is still 10 lx, although the physiological threshold for response to changes in photoperiod is closer to 2 lx. Very dim (0.05 lx) light filtering into blacked out houses will not stimulate the hypothalamic receptors responsible for photo-sexual responses, but may affect the bird's biological clock, which can alter its response to a constant short photoperiod. Feed intake shows a curvilinear dependence on environmental temperature. At temperatures below the panting threshold, performance can be maintained by adjusting the feed so as to maintain an adequate intake of critical amino acids. Above the panting threshold, the hen is unable to take in enough energy to maintain normal output. There is no dietary modification which can effectively offset this problem. Diurnally cycling temperatures result in feed intake and egg production equivalent to that observed under a constant temperature equal to the mean of the cycle. When the poultry house is cooler at night than by day, it helps to provide light so that the birds can feed during the cooler part of the cycle.

Large punctuational contribution of speciation to evolutionary divergence at the molecular level

A long-standing debate in evolutionary biology concerns whether species diverge gradually through time or by punctuational episodes at the time of speciation. We found that approximately 22% of substitutional changes at the DNA level can be attributed to punctuational evolution, and the remainder accumulates from background gradual divergence. Punctuational effects occur at more than twice the rate in plants and fungi than in animals, but the proportion of total divergence attributable to punctuational change does not vary among these groups. Punctuational changes cause departures from a clock-like tempo of evolution, suggesting that they should be accounted for in deriving dates from phylogenies. Punctuational episodes of evolution may play a larger role in promoting evolutionary divergence than has previously been appreciated.

Detecting the node-density artifact in phylogeny reconstruction

The node-density effect is an artifact of phylogeny reconstruction that can cause branch lengths to be underestimated in areas of the tree with fewer taxa. Webster, Payne, and Pagel (2003, Science 301:478) introduced a statistical procedure (the "delta" test) to detect this artifact, and here we report the results of computer simulations that examine the test's performance. In a sample of 50,000 random data sets, we find that the delta test detects the artifact in 94.4% of cases in which it is present. When the artifact is not present (n = 10,000 simulated data sets) the test showed a type I error rate of approximately 1.69%, incorrectly reporting the artifact in 169 data sets. Three measures of tree shape or "balance" failed to predict the size of the node-density effect. This may reflect the relative homogeneity of our randomly generated topologies, but emphasizes that nearly any topology can suffer from the artifact, the effect not being confined only to highly unevenly sampled or otherwise imbalanced trees. The ability to screen phylogenies for the node-density artifact is important for phylogenetic inference and for researchers using phylogenetic trees to infer evolutionary processes, including their use in molecular clock dating. [Delta test; molecular clock; molecular evolution; node-density effect; phylogenetic reconstruction; speciation; simulation.]

The effect of Parkinson's disease on time estimation as a function of stimulus duration range and modality

The present research sought to investigate the role of the basal ganglia in timing of sub- and supra-second intervals via an examination of the ability of people with Parkinson's disease (PD) to make temporal judgments in two ranges, 100-500 ms, and 1-5 s. Eighteen nondemented medicated patients with PD were compared with 14 matched controls on a duration-bisection task in which participants were required to discriminate auditory and visual signal durations within each time range. Results showed that patients with PD exhibited more variable duration judgments across both signal modality and duration range than controls, although closer analyses confirmed a timing deficit in the longer duration range only. The findings presented here suggest the bisection procedure may be a useful tool in identifying timing impairments in PD and, more generally, reaffirm the hypothesised role of the basal ganglia in temporal perception at the level of the attentionally mediated internal clock as well as memory retrieval and/or decision-making processes. (c) 2007 Elsevier Inc. All rights reserved.

How the brain blinks: towards a neurocognitive model of the attentional blink

When people monitor a visual stream of rapidly presented stimuli for two targets (T1 and T2), they often miss T2 if it falls into a time window of about half a second after T1 onset-the attentional blink (AB). We provide an overview of recent neuroscientific studies devoted to analyze the neural processes underlying the AB and their temporal dynamics. The available evidence points to an attentional network involving temporal, right-parietal and frontal cortex, and suggests that the components of this neural network interact by means of synchronization and stimulus-induced desynchronization in the beta frequency range. We set up a neurocognitive scenario describing how the AB might emerge and why it depends on the presence of masks and the other event(s) the targets are embedded in. The scenario supports the idea that the AB arises from "biased competition", with the top-down bias being generated by parietal-frontal interactions and the competition taking place between stimulus codes in temporal cortex.

Investigation into low power of a 2D Inverse Discrete CosineTransform (IDCT) in FPGAs

Design for low power in FPGA is rather limited since technology factors affecting power are either fixed or limited for FPGA families. This paper investigates opportunities for power savings of a pipelined 2D IDCT design at the architecture and logic level. We report power consumption savings of over 25% achieved in FPGA circuits obtained from clock gating implementation of optimizations made at the algorithmic level(1).

Power performance with gated clocks of a pipelined Cordic Core

This paper presents the evaluation in power consumption of gated clocks pipelined circuits with different register configurations in Virtex-based FPGA devices. Power impact of a gated clock circuitry aimed at reducing flip-flops output rate at the bit level is studied. Power performance is also given for pipeline stages based on the implementation of a double edge-triggered flip-flop. Using a pipelined Cordic Core circuit as an example, this study did not find evidence in power benefits either when gated clock at the bit-level or double-edge triggered flip-flops used when synthesized with FPGA logic resources.

A new organization for a perceptron-based branch predictor and its FPGA implementation

An unaltered rearrangement of the original computation of a neural based predictor at the algorithmic level is introduced as a new organization. Its FPGA implementation generates circuits that are 1.7 faster than a direct implementation of the original algorithm. This faster clock rate allows to implement predictors with longer history lengths using the nearly the same hardware budget.

Modeling the effects of node heterogeneity on the performance of a real grid application

The performance benefit when using Grid systems comes from different strategies, among which partitioning the applications into parallel tasks is the most important. However, in most cases the enhancement coming from partitioning is smoothed by the effect of the synchronization overhead, mainly due to the high variability of completion times of the different tasks, which, in turn, is due to the large heterogeneity of Grid nodes. For this reason, it is important to have models which capture the performance of such systems. In this paper we describe a queueing-network-based performance model able to accurately analyze Grid architectures, and we use the model to study a real parallel application executed in a Grid. The proposed model improves the classical modelling techniques and highlights the impact of resource heterogeneity and network latency on the application performance.

A clocking technique for FPGA pipelined designs

This paper presents a clocking pipeline technique referred to as a single-pulse pipeline (PP-Pipeline) and applies it to the problem of mapping pipelined circuits to a Field Programmable Gate Array (FPGA). A PP-pipeline replicates the operation of asynchronous micropipelined control mechanisms using synchronous-orientated logic resources commonly found in FPGA devices. Consequently, circuits with an asynchronous-like pipeline operation can be efficiently synthesized using a synchronous design methodology. The technique can be extended to include data-completion circuitry to take advantage of variable data-completion processing time in synchronous pipelined designs. It is also shown that the PP-pipeline reduces the clock tree power consumption of pipelined circuits. These potential applications are demonstrated by post-synthesis simulation of FPGA circuits. (C) 2004 Elsevier B.V. All rights reserved.

Modeling the effects of node heterogeneity on the performance of grid applications

The performance benefit when using grid systems comes from different strategies, among which partitioning the applications into parallel tasks is the most important. However, in most cases the enhancement coming from partitioning is smoothed by the effects of synchronization overheads, mainly due to the high variability in the execution times of the different tasks, which, in turn, is accentuated by the large heterogeneity of grid nodes. In this paper we design hierarchical, queuing network performance models able to accurately analyze grid architectures and applications. Thanks to the model results, we introduce a new allocation policy based on a combination between task partitioning and task replication. The models are used to study two real applications and to evaluate the performance benefits obtained with allocation policies based on task replication.

A parallel convolutional coder including embedded puncturing with application to consumer devices

As consumers demand more functionality) from their electronic devices and manufacturers supply the demand then electrical power and clock requirements tend to increase, however reassessing system architecture can fortunately lead to suitable counter reductions. To maintain low clock rates and therefore reduce electrical power, this paper presents a parallel convolutional coder for the transmit side in many wireless consumer devices. The coder accepts a parallel data input and directly computes punctured convolutional codes without the need for a separate puncturing operation while the coded bits are available at the output of the coder in a parallel fashion. Also as the computation is in parallel then the coder can be clocked at 7 times slower than the conventional shift-register based convolutional coder (using DVB 7/8 rate). The presented coder is directly relevant to the design of modern low-power consumer devices