Preparation and Characterization ofHigh-k Aluminum Oxide Thin Films by Atomic Layer Deposition for Gate Dielectric Applications

Present work deals with the Preparation and characterization of high-k aluminum oxide thin films by atomic layer deposition for gate dielectric applications.The ever-increasing demand for functionality and speed for semiconductor applications requires enhanced performance, which is achieved by the continuous miniaturization of CMOS dimensions. Because of this miniaturization, several parameters, such as the dielectric thickness, come within reach of their physical limit. As the required oxide thickness approaches the sub- l nm range, SiO 2 become unsuitable as a gate dielectric because its limited physical thickness results in excessive leakage current through the gate stack, affecting the long-term reliability of the device. This leakage issue is solved in the 45 mn technology node by the integration of high-k based gate dielectrics, as their higher k-value allows a physically thicker layer while targeting the same capacitance and Equivalent Oxide Thickness (EOT). Moreover, Intel announced that Atomic Layer Deposition (ALD) would be applied to grow these materials on the Si substrate. ALD is based on the sequential use of self-limiting surface reactions of a metallic and oxidizing precursor. This self-limiting feature allows control of material growth and properties at the atomic level, which makes ALD well-suited for the deposition of highly uniform and conformal layers in CMOS devices, even if these have challenging 3D topologies with high aspect-ratios. ALD has currently acquired the status of state-of-the-art and most preferred deposition technique, for producing nano layers of various materials of technological importance. This technique can be adapted to different situations where precision in thickness and perfection in structures are required, especially in the microelectronic scenario.

Microwave Plasma Assisted ALD Development for the Deposition of Gate Oxides & ALD of High-k Dielectrics

The semiconductor industry's urge towards faster, smaller and cheaper integrated circuits has lead the industry to smaller node devices. The integrated circuits that are now under volume production belong to 22 nm and 14 nm technology nodes. In 2007 the 45 nm technology came with the revolutionary high- /metal gate structure. 22 nm technology utilizes fully depleted tri-gate transistor structure. The 14 nm technology is a continuation of the 22 nm technology. Intel is using second generation tri-gate technology in 14 nm devices. After 14 nm, the semiconductor industry is expected to continue the scaling with 10 nm devices followed by 7 nm. Recently, IBM has announced successful production of 7 nm node test chips. This is the fashion how nanoelectronics industry is proceeding with its scaling trend. For the present node of technologies selective deposition and selective removal of the materials are required. Atomic layer deposition and the atomic layer etching are the respective techniques used for selective deposition and selective removal. Atomic layer deposition still remains as a futuristic manufacturing approach that deposits materials and lms in exact places. In addition to the nano/microelectronics industry, ALD is also widening its application areas and acceptance. The usage of ALD equipments in industry exhibits a diversi cation trend. With this trend, large area, batch processing, particle ALD and plasma enhanced like ALD equipments are becoming prominent in industrial applications. In this work, the development of an atomic layer deposition tool with microwave plasma capability is described, which is a ordable even for lightly funded research labs.

Analysis and Design of an Adaptive Polynomial Predistorter with the Loop Delay Estimator

Most adaptive linearization circuits for the nonlinear amplifier have a feedback loop that returns the output signal oj'tne eunplifier to the lineurizer. The loop delay of the linearizer most be controlled precisely so that the convergence of the linearizer should be assured lot this Letter a delay control circuit is presented. It is a delay lock loop (ULL) with it modified early-lute gate and can he easily applied to a DSP implementation. The proposed DLL circuit is applied to an adaptive linearizer with the use of a polynomial predistorter, and the simulalion for a 16-QAM signal is performed. The simulation results show that the proposed DLL eliminates the delay between the reference input signal and the delayed feedback signal of the linearizing circuit perfectly, so that the predistorter polynomial coefficients converge into the optimum value and a high degree of linearization is achieved

Laser-induced Bessel beams can realize fast all-optical switching in gold nanosol prepared by pulsed laser ablation

We demonstrate the possibility of realizing, all-optical switching in gold nanosol. Two overlapping laser beams are used for this purpose, due to which a low-power beam passing collinear to a high-power beam will undergo cross phase modulation and thereby distort the spatial profile. This is taken to advantage for performing logic operations. We have also measured the threshold pump power to obtain a NOT gate and the minimum response time of the device. Contrary to the general notion that the response time of thermal effects used in this application is of the order of milliseconds, we prove that short pump pulses can result in fast switching. Different combinations of beam splitters and combiners will lead to the formation of other logic functions too.

Investigations on the structural, optical and Magnetic properties of nanostructured cerium oxide in pure and doped forms and its polymer nanocomposiets

This thesis Entitled INVESTIGATIONS ON THE STRUCTURAL, OPTICAL AND MAGNETIC PROPERTIES OF NANOSTRUCTURED CERIUM OXIDE IN PURE AND DOPED FORMS AND ITS POLYMER NANOCOMPOSITES.Synthesis and processing of nanomatelials and nanostmctures are the essential aspects of nanotechnology. Studies on new physical properties and applications of nanomaterials and nanostructures are possible only when nanostructured materials are made available with desired size, morphology,crystal structure and chemical composition.Recently, several methods have been developed to prepare pure and doped CeO2 powder, including wet chemical synthesis, thermal hydrolysis, flux method, hydrothermal synthesis, gas condensation method, microwave technique etc. In all these, some special reaction conditions, such as high temperature, high pressure, capping agents, expensive or toxic solvents etc. have been involved.Another hi gh-li ght of the present work is room temperature ferromagnetism in cerium oxdie thin films deposited by spray pyrolysis technique.The observation of self trapped exciton mediated PL in ceria nanocrystals is another important outcome of the present study. STE mediated mechanism has been proposed for CeO2 nanocrystals based on the dependence of PL intensity on the annealing temperature. It would be interesting to extent these investigations to the doped forms of cerium oxide and cerium oxide thin films to get deeper Insight into STE mechanism.Due to time constraints detailed investigations could not be canied out on the preparation and properties of free standing films of polymer/ceria nanocomposites. It has been observed that good quality free standing films of PVDF/ceria, PS/C61‘l8, PMMA/ceria can be obtained using solution casting technique. These polymer nanocomposite films show high dielectric constant around 20 and offer prospects of applications as gate electrodes in metal-oxide semiconductor devices.

Fault Tolerant Error Coding and Detection using Reversible Gates

In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, quantum computing and nanotechnology. Low power circuits implemented using reversible logic that provides single error correction – double error detection (SEC-DED) is proposed in this paper. The design is done using a new 4 x 4 reversible gate called ‘HCG’ for implementing hamming error coding and detection circuits. A parity preserving HCG (PPHCG) that preserves the input parity at the output bits is used for achieving fault tolerance for the hamming error coding and detection circuits.