Performance analysis of double digit decimal multiplier on various FPGA logic families

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of (n / 2) 1 cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard

Characterizations of distributions using log odds rate

In this paper, we examine the relationships between log odds rate and various reliability measures such as hazard rate and reversed hazard rate in the context of repairable systems. We also prove characterization theorems for some families of distributions viz. Burr, Pearson and log exponential models. We discuss the properties and applications of log odds rate in weighted models. Further we extend the concept to the bivariate set up and study its properties.