Performance analysis of double digit decimal multiplier on various FPGA logic families

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of (n / 2) 1 cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard

High performance, low latency double digit decimal multiplier on ASIC and FPGA

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754- 2008 standard.

Performance Analysis of Reversible Fast Decimal Adders

This paper presents a performance analysis of reversible, fault tolerant VLSI implementations of carry select and hybrid decimal adders suitable for multi-digit BCD addition. The designs enable partial parallel processing of all digits that perform high-speed addition in decimal domain. When the number of digits is more than 25 the hybrid decimal adder can operate 5 times faster than conventional decimal adder using classical logic gates. The speed up factor of hybrid adder increases above 10 when the number of decimal digits is more than 25 for reversible logic implementation. Such highspeed decimal adders find applications in real time processors and internet-based applications. The implementations use only reversible conservative Fredkin gates, which make it suitable for VLSI circuits.

Diversity and effectiveness of tropical mangrove soil microflora on the degradation of polythene carry bags

The diversity and load of heterotrophic bacteria and fungi associated with the mangrove soil from Suva, Fiji Islands, was determined by using the plate count method. The ability of the bacterial isolates to produce various hydrolytic enzymes such as amylase, gelatinase and lipase were determined using the plate assay. The heterotrophic bacterial load was considerably higher than the fungal load. There was a predominance of the gram positive genus, Bacillus. Other genera encountered included Staphylococcus, Micrococcus, Listeria and Vibrio. Their effectiveness on the degradation of commercial polythene carry bags made of high density polyethylene (HDPE) and low density polyethylene (LDPE) was studied over a period of eight weeks in the laboratory. Biodegradation was measured in terms of mean weight loss, which was nearly 5 % after a period of eight weeks. There was a significant increase in the bacterial load of the soil attached to class 2 (HDPE) polythene. After eight weeks of submergence in mangrove soil, soil attached to class 1 and class 3 polythene mostly had Bacillus (Staphylococcus predominated in class 2 polythene). While most of the isolates were capable of producing hydrolytic enzymes such as amylase and gelatinase, lipolytic activity was low. Class 2 HDPE suffered the greatest biodegradation.