Decimal Multiplication using compact BCD Multiplier

Decimal multiplication is an integral part offinancial, commercial, and internet-based computations. The basic building block of a decimal multiplier is a single digit multiplier. It accepts two Binary Coded Decimal (BCD) inputs and gives a product in the range [0, 81] represented by two BCD digits. A novel design for single digit decimal multiplication that reduces the critical path delay and area is proposed in this research. Out of the possible 256 combinations for the 8-bit input, only hundred combinations are valid BCD inputs. In the hundred valid combinations only four combinations require 4 x 4 multiplication, combinations need x multiplication, and the remaining combinations use either x or x 3 multiplication. The proposed design makes use of this property. This design leads to more regular VLSI implementation, and does not require special registers for storing easy multiples. This is a fully parallel multiplier utilizing only combinational logic, and is extended to a Hex/Decimal multiplier that gives either a decimal output or a binary output. The accumulation ofpartial products generated using single digit multipliers is done by an array of multi-operand BCD adders for an (n-digit x n-digit) multiplication.

Fixed Point Decimal Multiplication Using RPS Algorithm

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. A novel design for single digit decimal multiplication that reduces the critical path delay and area for an iterative multiplier is proposed in this research. The partial products are generated using single digit multipliers, and are accumulated based on a novel RPS algorithm. This design uses n single digit multipliers for an n × n multiplication. The latency for the multiplication of two n-digit Binary Coded Decimal (BCD) operands is (n + 1) cycles and a new multiplication can begin every n cycle. The accumulation of final partial products and the first iteration of partial product generation for next set of inputs are done simultaneously. This iterative decimal multiplier offers low latency and high throughput, and can be extended for decimal floating-point multiplication.

Design and synthesis of efficient mac architectures for high speed decimal processor

Most of the commercial and financial data are stored in decimal fonn. Recently, support for decimal arithmetic has received increased attention due to the growing importance in financial analysis, banking, tax calculation, currency conversion, insurance, telephone billing and accounting. Performing decimal arithmetic with systems that do not support decimal computations may give a result with representation error, conversion error, and/or rounding error. In this world of precision, such errors are no more tolerable. The errors can be eliminated and better accuracy can be achieved if decimal computations are done using Decimal Floating Point (DFP) units. But the floating-point arithmetic units in today's general-purpose microprocessors are based on the binary number system, and the decimal computations are done using binary arithmetic. Only few common decimal numbers can be exactly represented in Binary Floating Point (BF P). ln many; cases, the law requires that results generated from financial calculations performed on a computer should exactly match with manual calculations. Currently many applications involving fractional decimal data perform decimal computations either in software or with a combination of software and hardware. The performance can be dramatically improved by complete hardware DFP units and this leads to the design of processors that include DF P hardware.VLSI implementations using same modular building blocks can decrease system design and manufacturing cost. A multiplexer realization is a natural choice from the viewpoint of cost and speed.This thesis focuses on the design and synthesis of efficient decimal MAC (Multiply ACeumulate) architecture for high speed decimal processors based on IEEE Standard for Floating-point Arithmetic (IEEE 754-2008). The research goal is to design and synthesize deeimal'MAC architectures to achieve higher performance.Efficient design methods and architectures are developed for a high performance DFP MAC unit as part of this research.

Dynamic mechanical analysis of binary and ternary polymer blends based on nylon copolymer/EPDM rubber and EPM grafted maleic anhydride compatibilizer

The dynamic mechanical properties such as storage modulus, loss modulus and damping properties of blends of nylon copolymer (PA6,66) with ethylene propylene diene (EPDM) rubber was investigated with special reference to the effect of blend ratio and compatibilisation over a temperature range –100°C to 150°C at different frequencies. The effect of change in the composition of the polymer blends on tanδ was studied to understand the extent of polymer miscibility and damping characteristics. The loss tangent curve of the blends exhibited two transition peaks, corresponding to the glass transition temperature (Tg) of individual components indicating incompatibility of the blend systems. The morphology of the blends has been examined by using scanning electron microscopy. The Arrhenius relationship was used to calculate the activation energy for the glass transition of the blends. Finally, attempts have been made to compare the experimental data with theoretical models.

Studies on New Binary Accelerator Systems in Rubber Vulcanisation

Department of Polymer Science and Rubber Technology, Cochin University of Science and Technology

Acid-Base, Surface electron donating and catalytic properties of binary oxides of Zr with rare earth elements

Department of Applied Chemistry, Cochin University of Science and Technology

Acid base characteristics of binary oxides of Zr with Ce and La

The surface acidity and basicity of binary oxides of Zr with Ce and La are determined using a series of Hammet indicators and Ho,,max values are reported. The generation of new acid sites habe been ascribed to the charge imbalance of M1-O-M2 bonds, where M1 and M2 are metal atoms. Both Bronsted and Lewis acid sites contribute to the acidity of the oxides

Study on acceleratore in rubber vulcanization with special reference to the binary systems containing substituted dithiobiurets

The thesis entitled Study on Accelerators in Rubber Vulcanization with Special Reference to the Binary Systems Containing Substituted Dithiobiurets. It includes a detailed study on the binary accelerator systems containing substituted dithiobiurets in natural rubber and NR latex and dithiobiurets in SBR and NR-SBR blends vulcanization systems. It deals with the experimental procedure adopted for the preparation of DTB-II and DTB-III; the procedure for compounding and vulcanization and determination of physical properties like modulus, tensile strength, elongation at break, hardness, compression set, heat build up etc. The results indicate that there is efficient acceleration activity of the dithiobiurets in the vulcanization of natural rubber latex containing TMT. The study of dithiobiurets in natural rubber and NR latex reveal that they are having definite accelerating effect in SBR vulcanization systems.

Acid-Base. Surface Electron Donatin6 &.Catai.Ytlc Properties Of Some Binary Mixed Oxides Containing Rare Earth Elements

Catalysis research underpins the science of modern chemical processing and fuel technologies. Catalysis is commercially one of the most important technologies in national economies. Solid state heterogeneous catalyst materials such as metal oxides and metal particles on ceramic oxide substrates are most common. They are typically used with commodity gases and liquid reactants. Selective oxidation catalysts of hydrocarbon feedstocks is the dominant process of converting them to key industrial chemicals, polymers and energy sources.[1] In the absence of a unique successfiil theory of heterogeneous catalysis, attempts are being made to correlate catalytic activity with some specific properties of the solid surface. Such correlations help to narrow down the search for a good catalyst for a given reaction. The heterogeneous catalytic performance of material depends on many factors such as [2] Crystal and surface structure of the catalyst. Thermodynamic stability of the catalyst and the reactant. Acid- base properties of the solid surface. Surface defect properties of the catalyst.Electronic and semiconducting properties and the band structure. Co-existence of dilferent types of ions or structures. Adsorption sites and adsorbed species such as oxygen.Preparation method of catalyst , surface area and nature of heat treatment. Molecular structure of the reactants. Many systematic investigations have been performed to correlate catalytic performances with the above mentioned properties. Many of these investigations remain isolated and further research is needed to bridge the gap in the present knowledge of the field.

A new look at reversible logic implementation of decimal adder

Reversibility plays a fundamental role when logic gates such as AND, OR, and XOR are not reversible. computations with minimal energy dissipation are considered. Hence, these gates dissipate heat and may reduce the life of In recent years, reversible logic has emerged as one of the most the circuit. So, reversible logic is in demand in power aware important approaches for power optimization with its circuits. application in low power CMOS, quantum computing and A reversible conventional BCD adder was proposed in using conventional reversible gates.

Performance analysis of double digit decimal multiplier on various FPGA logic families

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of (n / 2) 1 cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard

High performance, low latency double digit decimal multiplier on ASIC and FPGA

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754- 2008 standard.

Performance Analysis of Reversible Fast Decimal Adders

This paper presents a performance analysis of reversible, fault tolerant VLSI implementations of carry select and hybrid decimal adders suitable for multi-digit BCD addition. The designs enable partial parallel processing of all digits that perform high-speed addition in decimal domain. When the number of digits is more than 25 the hybrid decimal adder can operate 5 times faster than conventional decimal adder using classical logic gates. The speed up factor of hybrid adder increases above 10 when the number of decimal digits is more than 25 for reversible logic implementation. Such highspeed decimal adders find applications in real time processors and internet-based applications. The implementations use only reversible conservative Fredkin gates, which make it suitable for VLSI circuits.