Hakeperävaunun rungon esikorotuksen määritys

Hakeperävaunun rungon esikorotuksen suuruutta laskennallisesti ei ollut aiemmin määritet-ty Konepaja Antti Ranta Oy:ssä. Hakeperävaunun runko on valmistettu teräksestä. Tutki-muksessa luoduilla laskentamalleilla selvitettiin viisiakselisen hakeperävaunun rungon pys-tysuuntainen taipuma kuormitettuna. Tutkimus suoritettiin laskemalla hakeperävaunun pystysuuntainen siirtymä 42 tonnin ja 36 tonnin kokonaismassojen kuormituksilla hakeperävaunun rungon pituuden suhteen. Käsin-laskentamenetelmä on tässä tutkimuksessa englannin kieliseltä nimeltään conjugate beam method, suoraan käännettynä konjugaattipalkkimenetelmä. FE-analyysia sovellettiin kah-della eri laskentamallilla; käsinlaskentaa vertailevalla ja todellista hakeperävaunun runkoa vertailevilla FE-analyyseilla. Tutkimuksessa käytettyjen eri laskentatapojen tulokset vastasivat toisiaan sekä 42 tonnin että 36 tonnin kokonaismassojen kuormituksilla. Esikorotus määritettiin 42 tonnin koko-naismassalla kuormitetun todellista hakeperävaunun runkoa vastaavan 3D-mallin pysty-suuntaisesta taipumasta, josta luotiin esikorotettu hakeperävaunun rungon 3D-malli. Tutkimuksessa kehitettyjä laskentamalleja voidaan tulevaisuudessa käyttää yrityksen tuo-tekehityksessä. Esikorotuksella voidaan kompensoida pystysuuntaista taipumaa, jos esiko-rotuksesta ei ole haittaa itse rakenteelle.

Hakeperävaunun aerodynamiikan parantaminen

Raskaankaluston ajoneuvojen aerodynaaminen kehitys on kulkenut väärään suuntaan jo vuosisadan verran ja niiden muodon määräävä tekijä on kuljetustilan maksimointi ja toi-minnallisuus. Lähiaikoina on astumassa EU:ssa uusi direktiivi voimaan, joka sallii lisämas-san käyttämisen aerodynaamisiin lisäosiin. Työn tarkoituksena on tutkia mahdollisuuksia parantaa hakeperävaunun aerodynamiikkaa yksinkertaisilla lisäosilla. Työ on rajattu koskemaan perävaununetuosaan, -sivuosaan ja -pohjaan. Lisäksi rajoitteita asettaa Suomenlainsäädäntö ja EU:n direktiivit. Työssä perehdytään ilmanvastusvoiman syntymekanismeihin raskaankaluston ajoneuvojen kannalta ja käydään läpi merkittävimmät vaikuttavat tekijät ilmanvastusvoimiin sekä kuorma-auton perävaunun eri muotojen ja osien vaikutus. Perävaunuun asetettavien il-manohjaimien vaikutukset ja toiminta selvitetään. Avainasemassa hakeperävaunun aerodynamiikan parantamisessa on ilmavirtauksen estä-minen perävaunun alle sekä etupuolelta. Lisäksi virtausten muuttamien perävaunun takana on hyödyllistä. Merkittävimmät hyödyt saadaan niistä ratkaisuista, jotka estävät ilman virtausta perävau-nun alle sekä renkaisiin. Näitä ratkaisuja olivat sivuhelmat ja pohjan sekä renkaiden kote-lointi. Lisäksi ilmavirtauksen estäminen perävaunun edestä tuotti merkittävää hyötyä. Levy perävaunun välissä tai koko välin peittämällä saadaan aikaan huomattavaa vähenemistä ilmanvastuksessa.

Metsäpolttoaineiden vesitiekuljetus proomukalustolla

Metsäpolttoaineiden käyttö kasvaa lämpö- ja voimalaitoksissa ja mahdollisissa biojalostamoissa. Metsäpolttoaineilla voidaan saavuttaa päästövähennyksiä korvaamalla päästöintensiivisempiä polttoaineita. Metsäpolttoaineen kysynnän kasvu suurkäyttöpaikoilla luo uusia vaatimuksia metsäbiomassan hankintaan. Metsäpolttoaineiden vesitiekuljetuksen sisältämiä logistiikkajärjestelmiä kehittämällä toimitusvarmuutta pystytään parantamaan ja hankintaa laajentamaan kustannustehokkaasti ja ympäristöystävällisesti. Kuljetuskokeilut antoivat uutta tietoa vesitiekuljetuksen sisältämästä hankinnasta. Lastikapasiteetti nykyisen kaltaisessa Eurooppa IIa -suurproomussa vaihtelee 1200 tonnista jopa 1800 tonniin (kosteus 40 %) riippuen tiivistymisestä ja proomun modifiointiasteesta. Metsähakkeen energiatiheys oli suurproomukuljetuksissa keskimäärin 1 MWh/i-m3, joka oli 25 % parempi kuin vertailun hakerekkakuljetuksissa. Vesitiekuljetuksen kustannukset olivat kuljetuskokeiluissa lastauksineen ja purkuineen 0,02 €/MWh/km, ollen noin 20 % ketjun kokonaiskustannuksista. Simuloinnin edullisimpien vesitiekuljetusvaihtoehtojen vaihteluvälin kustannukset olivat vastaavasti 0,013 - 0,026 €/MWh/km. Lastauksen ja purun kustannus oli 0,4 - 0,6 €/MWh ja vesitiekuljetus 0,9 - 2,0 €/MWh (100 km). Ketjun kokonaiskustannukset hakkuutähdehakkeelle vaihtelivat simuloinnin edullisimpien vaihtoehtojen perusteella välillä 10,8 - 12,1 €/MWh (30 km rekka, 100 km proomu). Kuljetusketjujen simuloinnin kustannukset osoittivat proomukuljetusketjun olevan kilpailukykyinen vaihtoehto hakerekkakuljetusketjulle kalustosta ja vuosittaisista käyttötunneista riippuen kuljetusetäisyyden ylittäessä 100 km. Kustannustehokkain ratkaisu vesitiekuljetuksessa saavutettiin pienen aluksen ja suuren kokoluokan proomuyksikön kytkyeellä. Haketus kannattaa toteuttaa ennen proomukuljetuksen osuutta metsähakkeen paremman tiiviyden ja käsiteltävyyden perusteella. Logistiikkajärjestelmiä pitää kehittää tapauskohtaisesti käyttöpaikan tarpeet ja olosuhteet huomioon ottaen. Metsäpolttoaineiden vesitiekuljetuksen sisältämän logistiikan liiketoimintamallien vertailussa arvioitiin vaihtoehtoiset ulkoistetut toimintamallit paremmaksi kuin nykyinen urakointimalli. Tämä mahdollistaa paremman metsähakkeen saatavuuden ja logistiikan tehokkuuden lastausterminaaleissa. Terminaalitoiminnot ja proomukuljetukset lisäävät uusia liiketoimintamahdollisuuksia ja mahdollistavat metsäpolttoaineiden

On Fault Tolerance Methods for Networks-on-Chip

Technology scaling has proceeded into dimensions in which the reliability of manufactured devices is becoming endangered. The reliability decrease is a consequence of physical limitations, relative increase of variations, and decreasing noise margins, among others. A promising solution for bringing the reliability of circuits back to a desired level is the use of design methods which introduce tolerance against possible faults in an integrated circuit. This thesis studies and presents fault tolerance methods for network-onchip (NoC) which is a design paradigm targeted for very large systems-onchip. In a NoC resources, such as processors and memories, are connected to a communication network; comparable to the Internet. Fault tolerance in such a system can be achieved at many abstraction levels. The thesis studies the origin of faults in modern technologies and explains the classification to transient, intermittent and permanent faults. A survey of fault tolerance methods is presented to demonstrate the diversity of available methods. Networks-on-chip are approached by exploring their main design choices: the selection of a topology, routing protocol, and flow control method. Fault tolerance methods for NoCs are studied at different layers of the OSI reference model. The data link layer provides a reliable communication link over a physical channel. Error control coding is an efficient fault tolerance method especially against transient faults at this abstraction level. Error control coding methods suitable for on-chip communication are studied and their implementations presented. Error control coding loses its effectiveness in the presence of intermittent and permanent faults. Therefore, other solutions against them are presented. The introduction of spare wires and split transmissions are shown to provide good tolerance against intermittent and permanent errors and their combination to error control coding is illustrated. At the network layer positioned above the data link layer, fault tolerance can be achieved with the design of fault tolerant network topologies and routing algorithms. Both of these approaches are presented in the thesis together with realizations in the both categories. The thesis concludes that an optimal fault tolerance solution contains carefully co-designed elements from different abstraction levels

Formal Power Analysis of Systems-on-Chip

The design methods and languages targeted to modern System-on-Chip designs are facing tremendous pressure of the ever-increasing complexity, power, and speed requirements. To estimate any of these three metrics, there is a trade-off between accuracy and abstraction level of detail in which a system under design is analyzed. The more detailed the description, the more accurate the simulation will be, but, on the other hand, the more time consuming it will be. Moreover, a designer wants to make decisions as early as possible in the design flow to avoid costly design backtracking. To answer the challenges posed upon System-on-chip designs, this thesis introduces a formal, power aware framework, its development methods, and methods to constraint and analyze power consumption of the system under design. This thesis discusses on power analysis of synchronous and asynchronous systems not forgetting the communication aspects of these systems. The presented framework is built upon the Timed Action System formalism, which offer an environment to analyze and constraint the functional and temporal behavior of the system at high abstraction level. Furthermore, due to the complexity of System-on-Chip designs, the possibility to abstract unnecessary implementation details at higher abstraction levels is an essential part of the introduced design framework. With the encapsulation and abstraction techniques incorporated with the procedure based communication allows a designer to use the presented power aware framework in modeling these large scale systems. The introduced techniques also enable one to subdivide the development of communication and computation into own tasks. This property is taken into account in the power analysis part as well. Furthermore, the presented framework is developed in a way that it can be used throughout the design project. In other words, a designer is able to model and analyze systems from an abstract specification down to an implementable specification.

On the potential utilisation of sawdust and wood chip screenings

This work is based on the utilisation of sawdust and wood chip screenings for different purposes. A substantial amount of these byproducts are readily available in the Finnish forest industry. A black liquor impregnation study showed that sawdust-like wood material behaves differently from normal chips. Furthermore, the fractionation and removal of the smallest size fractions did not have a significant effect on the impregnation of sawdust-like wood material. Sawdust kraft cooking equipped with an impregnation stage increases the cooking yield and decreases the lignin content of the produced pulp. Impregnation also increases viscosity of the pulp and decreases chlorine dioxide consumption in bleaching. In addition, impregnation increases certain pulp properties after refining. Hydrotropic extraction showed that more lignin can be extracted from hardwood than softwood. However, the particle size had a major influence on the lignin extraction. It was possible to extract more lignin from spruce sawdust than spruce chips. Wood chip screenings are usually combusted to generate energy. They can also be used in the production of kraft pulp, ethanol and chemicals. It is not economical to produce ethanol from wood chip screenings because of the expensive wood material. Instead, they should be used for production of steam and energy, kraft pulp and higher value added chemicals. Bleached sawdust kraft pulp can be used to replace softwood kraft pulp in mechanical pulp based papers because it can improve certain physical properties. It is economically more feasible to use bleached sawdust kraft pulp in stead of softwood kraft pulp, especially when the reinforcement power requirement is moderate.

Modeling and Analysis of Noise and Interconnects for On-Chip Communication Link Design

This thesis considers modeling and analysis of noise and interconnects in onchip communication. Besides transistor count and speed, the capabilities of a modern design are often limited by on-chip communication links. These links typically consist of multiple interconnects that run parallel to each other for long distances between functional or memory blocks. Due to the scaling of technology, the interconnects have considerable electrical parasitics that affect their performance, power dissipation and signal integrity. Furthermore, because of electromagnetic coupling, the interconnects in the link need to be considered as an interacting group instead of as isolated signal paths. There is a need for accurate and computationally effective models in the early stages of the chip design process to assess or optimize issues affecting these interconnects. For this purpose, a set of analytical models is developed for on-chip data links in this thesis. First, a model is proposed for modeling crosstalk and intersymbol interference. The model takes into account the effects of inductance, initial states and bit sequences. Intersymbol interference is shown to affect crosstalk voltage and propagation delay depending on bus throughput and the amount of inductance. Next, a model is proposed for the switching current of a coupled bus. The model is combined with an existing model to evaluate power supply noise. The model is then applied to reduce both functional crosstalk and power supply noise caused by a bus as a trade-off with time. The proposed reduction method is shown to be effective in reducing long-range crosstalk noise. The effects of process variation on encoded signaling are then modeled. In encoded signaling, the input signals to a bus are encoded using additional signaling circuitry. The proposed model includes variation in both the signaling circuitry and in the wires to calculate the total delay variation of a bus. The model is applied to study level-encoded dual-rail and 1-of-4 signaling. In addition to regular voltage-mode and encoded voltage-mode signaling, current-mode signaling is a promising technique for global communication. A model for energy dissipation in RLC current-mode signaling is proposed in the thesis. The energy is derived separately for the driver, wire and receiver termination.

Exploring Adaptive Implementation of On-Chip Networks

As technology geometries have shrunk to the deep submicron regime, the communication delay and power consumption of global interconnections in high performance Multi- Processor Systems-on-Chip (MPSoCs) are becoming a major bottleneck. The Network-on- Chip (NoC) architecture paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues such as performance limitations of long interconnects and integration of large number of Processing Elements (PEs) on a chip. The choice of routing protocol and NoC structure can have a significant impact on performance and power consumption in on-chip networks. In addition, building a high performance, area and energy efficient on-chip network for multicore architectures requires a novel on-chip router allowing a larger network to be integrated on a single die with reduced power consumption. On top of that, network interfaces are employed to decouple computation resources from communication resources, to provide the synchronization between them, and to achieve backward compatibility with existing IP cores. Three adaptive routing algorithms are presented as a part of this thesis. The first presented routing protocol is a congestion-aware adaptive routing algorithm for 2D mesh NoCs which does not support multicast (one-to-many) traffic while the other two protocols are adaptive routing models supporting both unicast (one-to-one) and multicast traffic. A streamlined on-chip router architecture is also presented for avoiding congested areas in 2D mesh NoCs via employing efficient input and output selection. The output selection utilizes an adaptive routing algorithm based on the congestion condition of neighboring routers while the input selection allows packets to be serviced from each input port according to its congestion level. Moreover, in order to increase memory parallelism and bring compatibility with existing IP cores in network-based multiprocessor architectures, adaptive network interface architectures are presented to use multiple SDRAMs which can be accessed simultaneously. In addition, a smart memory controller is integrated in the adaptive network interface to improve the memory utilization and reduce both memory and network latencies. Three Dimensional Integrated Circuits (3D ICs) have been emerging as a viable candidate to achieve better performance and package density as compared to traditional 2D ICs. In addition, combining the benefits of 3D IC and NoC schemes provides a significant performance gain for 3D architectures. In recent years, inter-layer communication across multiple stacked layers (vertical channel) has attracted a lot of interest. In this thesis, a novel adaptive pipeline bus structure is proposed for inter-layer communication to improve the performance by reducing the delay and complexity of traditional bus arbitration. In addition, two mesh-based topologies for 3D architectures are also introduced to mitigate the inter-layer footprint and power dissipation on each layer with a small performance penalty.

On Dynamic Monitoring Methods for Networks-on-Chip

Rapid ongoing evolution of multiprocessors will lead to systems with hundreds of processing cores integrated in a single chip. An emerging challenge is the implementation of reliable and efficient interconnection between these cores as well as other components in the systems. Network-on-Chip is an interconnection approach which is intended to solve the performance bottleneck caused by traditional, poorly scalable communication structures such as buses. However, a large on-chip network involves issues related to congestion problems and system control, for instance. Additionally, faults can cause problems in multiprocessor systems. These faults can be transient faults, permanent manufacturing faults, or they can appear due to aging. To solve the emerging traffic management, controllability issues and to maintain system operation regardless of faults a monitoring system is needed. The monitoring system should be dynamically applicable to various purposes and it should fully cover the system under observation. In a large multiprocessor the distances between components can be relatively long. Therefore, the system should be designed so that the amount of energy-inefficient long-distance communication is minimized. This thesis presents a dynamically clustered distributed monitoring structure. The monitoring is distributed so that no centralized control is required for basic tasks such as traffic management and task mapping. To enable extensive analysis of different Network-on-Chip architectures, an in-house SystemC based simulation environment was implemented. It allows transaction level analysis without time consuming circuit level implementations during early design phases of novel architectures and features. The presented analysis shows that the dynamically clustered monitoring structure can be efficiently utilized for traffic management in faulty and congested Network-on-Chip-based multiprocessor systems. The monitoring structure can be also successfully applied for task mapping purposes. Furthermore, the analysis shows that the presented in-house simulation environment is flexible and practical tool for extensive Network-on-Chip architecture analysis.

Power cycling lifetime estimation of IGBT power modules based on chip temperature modeling

In this doctoral thesis, methods to estimate the expected power cycling life of power semiconductor modules based on chip temperature modeling are developed. Frequency converters operate under dynamic loads in most electric drives. The varying loads cause thermal expansion and contraction, which stresses the internal boundaries between the material layers in the power module. Eventually, the stress wears out the semiconductor modules. The wear-out cannot be detected by traditional temperature or current measurements inside the frequency converter. Therefore, it is important to develop a method to predict the end of the converter lifetime. The thesis concentrates on power-cycling-related failures of insulated gate bipolar transistors. Two types of power modules are discussed: a direct bonded copper (DBC) sandwich structure with and without a baseplate. Most common failure mechanisms are reviewed, and methods to improve the power cycling lifetime of the power modules are presented. Power cycling curves are determined for a module with a lead-free solder by accelerated power cycling tests. A lifetime model is selected and the parameters are updated based on the power cycling test results. According to the measurements, the factor of improvement in the power cycling lifetime of modern IGBT power modules is greater than 10 during the last decade. Also, it is noticed that a 10 C increase in the chip temperature cycle amplitude decreases the lifetime by 40%. A thermal model for the chip temperature estimation is developed. The model is based on power loss estimation of the chip from the output current of the frequency converter. The model is verified with a purpose-built test equipment, which allows simultaneous measurement and simulation of the chip temperature with an arbitrary load waveform. The measurement system is shown to be convenient for studying the thermal behavior of the chip. It is found that the thermal model has a 5 C accuracy in the temperature estimation. The temperature cycles that the power semiconductor chip has experienced are counted by the rainflow algorithm. The counted cycles are compared with the experimentally verified power cycling curves to estimate the life consumption based on the mission profile of the drive. The methods are validated by the lifetime estimation of a power module in a direct-driven wind turbine. The estimated lifetime of the IGBT power module in a direct-driven wind turbine is 15 000 years, if the turbine is located in south-eastern Finland.

Is it worth while driving without a trailer?

kuv., 22 x 31 cm