Design Space Exploration for MPSoC Architectures

Multiprocessor system-on-chip (MPSoC) designs utilize the available technology and communication architectures to meet the requirements of the upcoming applications. In MPSoC, the communication platform is both the key enabler, as well as the key differentiator for realizing efficient MPSoCs. It provides product differentiation to meet a diverse, multi-dimensional set of design constraints, including performance, power, energy, reconfigurability, scalability, cost, reliability and time-to-market. The communication resources of a single interconnection platform cannot be fully utilized by all kind of applications, such as the availability of higher communication bandwidth for computation but not data intensive applications is often unfeasible in the practical implementation. This thesis aims to perform the architecture-level design space exploration towards efficient and scalable resource utilization for MPSoC communication architecture. In order to meet the performance requirements within the design constraints, careful selection of MPSoC communication platform, resource aware partitioning and mapping of the application play important role. To enhance the utilization of communication resources, variety of techniques such as resource sharing, multicast to avoid re-transmission of identical data, and adaptive routing can be used. For implementation, these techniques should be customized according to the platform architecture. To address the resource utilization of MPSoC communication platforms, variety of architectures with different design parameters and performance levels, namely Segmented bus (SegBus), Network-on-Chip (NoC) and Three-Dimensional NoC (3D-NoC), are selected. Average packet latency and power consumption are the evaluation parameters for the proposed techniques. In conventional computing architectures, fault on a component makes the connected fault-free components inoperative. Resource sharing approach can utilize the fault-free components to retain the system performance by reducing the impact of faults. Design space exploration also guides to narrow down the selection of MPSoC architecture, which can meet the performance requirements with design constraints.

Transcriptional and Epigenetic Regulation of Human CD4+ T Helper Lineage Specification

Activated T helper (Th) cells have ability to differentiate into functionally distinct Th1, Th2 and Th17 subsets through a series of overlapping networks that include signaling and transcriptional control and the epigenetic mechanisms to direct immune responses. However, inappropriate execution in the differentiation process and abnormal function of these Th cells can lead to the development of several immune mediated diseases. Therefore, the thesis aimed at identifying genes and gene regulatory mechanisms responsible for Th17 differentiation and to study epigenetic changes associated with early stage of Th1/Th2 cell differentiation. Genome wide transcriptional profiling during early stages of human Th17 cell differentiation demonstrated differential regulation of several novel and currently known genes associated with Th17 differentiation. Selected candidate genes were further validated at protein level and their specificity for Th17 as compared to other T helper subsets was analyzed. Moreover, combination of RNA interference-mediated downregulation of gene expression, genome-wide transcriptome profiling and chromatin immunoprecipitation followed by massive parallel sequencing (ChIP-seq), combined with computational data integration lead to the identification of direct and indirect target genes of STAT3, which is a pivotal upstream transcription factor for Th17 cell polarization. Results indicated that STAT3 directly regulates the expression of several genes that are known to play a role in activation, differentiation, proliferation, and survival of Th17 cells. These results provide a basis for constructing a network regulating gene expression during early human Th17 differentiation. Th1 and Th2 lineage specific enhancers were identified from genome-wide maps of histone modifications generated from the cells differentiating towards Th1 and Th2 lineages at 72h. Further analysis of lineage-specific enhancers revealed known and novel transcription factors that potentially control lineage-specific gene expression. Finally, we found an overlap of a subset of enhancers with SNPs associated with autoimmune diseases through GWASs suggesting a potential role for enhancer elements in the disease development. In conclusion, the results obtained have extended our knowledge of Th differentiation and provided new mechanistic insights into dysregulation of Th cell differentiation in human immune mediated diseases.

Thermal-Aware Networked Many-Core Systems

Advancements in IC processing technology has led to the innovation and growth happening in the consumer electronics sector and the evolution of the IT infrastructure supporting this exponential growth. One of the most difficult obstacles to this growth is the removal of large amount of heatgenerated by the processing and communicating nodes on the system. The scaling down of technology and the increase in power density is posing a direct and consequential effect on the rise in temperature. This has resulted in the increase in cooling budgets, and affects both the life-time reliability and performance of the system. Hence, reducing on-chip temperatures has become a major design concern for modern microprocessors. This dissertation addresses the thermal challenges at different levels for both 2D planer and 3D stacked systems. It proposes a self-timed thermal monitoring strategy based on the liberal use of on-chip thermal sensors. This makes use of noise variation tolerant and leakage current based thermal sensing for monitoring purposes. In order to study thermal management issues from early design stages, accurate thermal modeling and analysis at design time is essential. In this regard, spatial temperature profile of the global Cu nanowire for on-chip interconnects has been analyzed. It presents a 3D thermal model of a multicore system in order to investigate the effects of hotspots and the placement of silicon die layers, on the thermal performance of a modern ip-chip package. For a 3D stacked system, the primary design goal is to maximise the performance within the given power and thermal envelopes. Hence, a thermally efficient routing strategy for 3D NoC-Bus hybrid architectures has been proposed to mitigate on-chip temperatures by herding most of the switching activity to the die which is closer to heat sink. Finally, an exploration of various thermal-aware placement approaches for both the 2D and 3D stacked systems has been presented. Various thermal models have been developed and thermal control metrics have been extracted. An efficient thermal-aware application mapping algorithm for a 2D NoC has been presented. It has been shown that the proposed mapping algorithm reduces the effective area reeling under high temperatures when compared to the state of the art.

Det hjemløse menneske : en studie av sykdom og lidelse

The overall aim of this study was to achieve a deeper understanding of the relationship between human suffering, disease and illness. The study is rooted in the health-care scientific research tradition as developed by Eriksson and her co-researchers at Åbo Akademi. The over-riding methodological initiative was Gadamer's hermeneutic philosophy. The main research question is: What is suffering of illness and disease? Sub-questions: Which characteristics occur when people experience being acutely ill (Article I)? What do the concepts acute, critical and chronic mean semantically (Article II)? In which way does the relation between the human being's experience of disease, illness and suffering, be manifested and understood? How does one characterize the relationship between the experience of contracting disease, illness and suffering (Article III)? How can the hermeneutical conversation contribute to the understanding of suffering caused by disease and illness (Article IV)? The results of sub-study 1 showed that patients with acute myocardial infarction saw themselves as coping, competent, and autonomous individuals. They were used to exercising control, and it was difficult for them to relinquish control. The semantic analysis of acute in sub-study 2 revealed that the concept acute has had an unclear content in the Norwegian language over the past 65 years. Acute, as a concept, says something about the way a situation arises, but not much about what it is that arises. In sub-study, 3 the relation between disease, illness and suffering is discussed. The expression of illness and suffering as verbs can convey more clearly what it is that occurs with persons who experience disease, illness and suffering. The discussion in sub-study 4 focuses on trustworthiness in hermeneutical studies.

Lean Duplex -terästen hitsaus

Viime vuosien aikana tapahtunut nikkelin hinnan nouseminen on vaikuttanut austeniittis-ferriittisten ruostumattomien terästen, ns. duplex -terästen kehittämiseen. Niukkaseosteisemmissa lean duplex -teräksissä seostetun nikkelin määrää on vähennetty ja sitä on korvattu typellä ja mangaanilla. Nämä muutokset ko. terästen seostuksessa aiheuttavat haasteita hitsaukselle, erityisesti austeniitti-ferriitti -suhteen säilyttämisessä, sekä sitä kautta iskusitkeyden ja korroosio-ominaisuuksien säilyttämiselle. Suurempi typen osuus myös lisää teräksen hitsisulan viskositeettia, mikä heikentää juuripalkojen hitsauksessa tunkeumaa. Tässsä diplomityössä on tutkittu keinoja helpottaa paksujen (yli 20 mm) lean duplex -teräslevyjen hitsausta käytännön näkökulmasta, sekä parantaa hitsattujen levyjen iskusitkeyttä. Hitsauskokeilla löydettiin hitsausta helpottavia menetelmiä ja kokeista saatiin karsimalla valikoitua hitsausarvot, joilla pystytään hitsaamaan painelaitedirektiivin mukaisesti hyväksyttäviä hitsejä lean duplex -laatuihin LDX2101 ja UR2202.

Jauhekaari- ja tandem-MIG/MAG-hitsauksen vertailu

Tässä kanditaatintyössä vertaillaan jauhekaari- ja tandem-MIG/MAG-hitsausta kirjallisuustutkimuksena. Vertailun kohteena ovat hitsausprosessien tuottavuus ja kustannukset sekä hitsausprosesseilla saavutettava laatu. Lisäksi kandidaatintyössä esitetään hitsausprosesseille tyypilliset käyttökohteet CASE -esimerkkeinä.

Choosing the target loci : heat shock factors HSF1 and HSF2 as regulators of cell stress and development

Heat shock factors (HSFs) are an evolutionarily well conserved family of transcription factors that coordinate stress-induced gene expression and direct versatile physiological processes in eukaryote organisms. The essentiality of HSFs for cellular homeostasis has been well demonstrated, mainly through HSF1-induced transcription of heat shock protein (HSP) genes. HSFs are important regulators of many fundamental processes such as gametogenesis, metabolic control and aging, and are involved in pathological conditions including cancer progression and neurodegenerative diseases. In each of the HSF-mediated processes, however, the detailed mechanisms of HSF family members and their complete set of target genes have remained unknown. Recently, rapid advances in chromatin studies have enabled genome-wide characterization of protein binding sites in a high resolution and in an unbiased manner. In this PhD thesis, these novel methods that base on chromatin immunoprecipitation (ChIP) are utilized and the genome-wide target loci for HSF1 and HSF2 are identified in cellular stress responses and in developmental processes. The thesis and its original publications characterize the individual and shared target genes of HSF1 and HSF2, describe HSF1 as a potent transactivator, and discover HSF2 as an epigenetic regulator that coordinates gene expression throughout the cell cycle progression. In male gametogenesis, novel physiological functions for HSF1 and HSF2 are revealed and HSFs are demonstrated to control the expression of X- and Y-chromosomal multicopy genes in a silenced chromatin environment. In stressed human cells, HSF1 and HSF2 are shown to coordinate the expression of a wide variety of genes including genes for chaperone machinery, ubiquitin, regulators of cell cycle progression and signaling. These results highlight the importance of cell type and cell cycle phase in transcriptional responses, reveal the myriad of processes that are adjusted in a stressed cell and describe novel mechanisms that maintain transcriptional memory in mitotic cell division.

Puuhakkeen käsittely- ja poltto-ominaisuuksien parantaminen

Nykyaikana yhteiskunta tavoittelee uusiutuvaa ja ympäristöä säästävää energiantuotantoa. Biopolttoaineiden käyttö vähentää fossiilisten polttoaineiden osuutta energiantuotannossa. Jotta biopolttoaineilla voidaan korvata fossiilisia polttoaineita, biopolttoaineita täytyy jalostaa. Tämän diplomityön tarkoituksena on selvittää puuhakkeen jalostuksen merkitystä hakkeen käytölle ja kannattavuudelle. Hakkeen kuivaamisella ja seulonnalla voidaan parantaa hakkeen käsittely- ja poltto-ominaisuuksia. Kosteuden ja tasalaatuisuuden merkitys suurenee, kun haketta käytetään pienissä kattiloissa. Pienissä kattiloissa lämmöntuotannon hyötysuhde pienenee merkittävästi kosteuden suurentuessa. Tällöin polttoaineen kulutus ja energiantuotantokustannukset suurenevat. Suuremmissa kattiloissa hyvälaatuisella hakkeella on mahdollista korvata kalliimpia vara- ja huippukuormapolttoaineita, kuten öljyä. Tällöin fossiilisten polttoaineiden osuus pienenee. Lisäksi kuivaaminen ja seulominen ovat edullisia jalostusprosesseja esimerkiksi pelletin tuotantoon verrattuna.

Tukin mittaus ja optimointi sahalinjassa

Tukin mittaus ennen sahausta ja sahausasetteen optimointi on kehittynyt paljon viimeisen 10 vuoden aikana. Sahauksen kannattavuuden huonontuessa raaka-aineen tehokas hyödyntäminen on muodostunut tärkeäksi osaksi prosessia. Mittalaitteiden tekniikan kehityttyä on ollut mahdollista mitata tukin muoto ja halkaisijat eri kohdista entistä tarkemmin. Sahausasetteen optimoinnilla pyritään raaka-aineen mahdollisimman tehokkaaseen käyttöön eli saamaan mahdollisimman hyvä saanto jokaisesta yksittäisestä sahatusta tukista. Mittaustarkkuus on suoraan kytköksissä sahausasetteen optimointi tuloksen onnistumiseen. Yleisesti tukin mittaus ennen sahausta ja sahausasetteen optimointi tulevat samalta toimittajalta. Työssä tarkasteltiin kahden eri toimittajan tukkimittareita sekä optimoinnin onnistumista sen perusteella. Käytössä oli lasikuituinen mallitukki, jota mitattiin kummankin toimittajan mittareilla. Näin voitiin suoraan vertailla mittauksen ja optimoinnin onnistumista ja verrata sitä optimaalisiin tuloksiin. Työssä käytettiin kandidaatintyössä luomaani toimintamallia tukkimittarin tarkkuuden toteamiseksi. Mittaus- ja optimointivirheistä pystyttiin laskemaan, kuinka paljon tappiota sahalaitokselle aiheutui verrattuna optimaaliseen mittaus- ja optimointitulokseen. Jo pienetkin virheet optimoinnissa ja mittauksessa vaikuttavat sahauksen kannattavuuteen, kun tarkastellaan sahalaitosta jossa sahataan 8000 – 10 000 tukkia yhden työvuoron aikana. Tulosten perusteella mittarit mittaavat hieman virheellisesti, ja kummankin mittarin mittausten perusteella saatiin eri sahausasete optimointitulokseksi. Mittavirheen takia voitiin todeta, että parantamalla mittaustarkkuutta voidaan sahauksen kannattavuutta parantaa.

Effects of the partial removal of wood hemicelluloses on the properties of kraft pulp

The objective of this work was to study the effects of partial removal of wood hemicelluloses on the properties of kraft pulp.The work was conducted by extracting hemicelluloses (1) by a softwood chip pretreatment process prior to kraft pulping, (2) by alkaline extraction from bleached birch kraft pulp, and (3) by enzymatic treatment, xylanase treatment in particular, of bleached birch kraft pulp. The qualitative and quantitative changes in fibers and paper properties were evaluated. In addition, the applicability of the extraction concepts and hemicellulose-extracted birch kraft pulp as a raw material in papermaking was evaluated in a pilot-scale papermaking environment. The results showed that each examined hemicellulose extraction method has its characteristic effects on fiber properties, seen as differences in both the physical and chemical nature of the fibers. A prehydrolysis process prior to the kraft pulping process offered reductions in cooking time, bleaching chemical consumption and produced fibers with low hemicellulose content that are more susceptible to mechanically induced damages and dislocations. Softwood chip pretreatment for hemicellulose recovery prior to cooking, whether acidic or alkaline, had an impact on the physical properties of the non-refined and refined pulp. In addition, all the pretreated pulps exhibited slower beating response than the unhydrolyzed reference pulp. Both alkaline extraction and enzymatic (xylanase) treatment of bleached birch kraft pulp fibers indicated very selective hemicellulose removal, particularly xylan removal. Furthermore, these two hemicellulose-extracted birch kraft pulps were utilized in a pilot-scale papermaking environment in order to evaluate the upscalability of the extraction concepts. Investigations made using pilot paper machine trials revealed that some amount of alkalineextracted birch kraft pulp, with a 24.9% reduction in the total amount of xylan, could be used in the papermaking stock as a mixture with non-extracted pulp when producing 75 g/m2 paper. For xylanase-treated fibers there were no reductions in the mechanical properties of the 180 g/m2 paper produced compared to paper made from the control pulp, although there was a 14.2% reduction in the total amount of xylan in the xylanase-treated pulp compared to the control birch kraft pulp. This work emphasized the importance of the hemicellulose extraction method in providing new solutions to create functional fibers and in providing a valuable hemicellulose co-product stream. The hemicellulose removal concept therefore plays an important role in the integrated forest biorefinery scenario, where the target is to the co-production of hemicellulose-extracted pulp and hemicellulose-based chemicals or fuels.

Potential and Challenges of Analog Reconfigurable Computation in Modern and Future CMOS

In this work, the feasibility of the floating-gate technology in analog computing platforms in a scaled down general-purpose CMOS technology is considered. When the technology is scaled down the performance of analog circuits tends to get worse because the process parameters are optimized for digital transistors and the scaling involves the reduction of supply voltages. Generally, the challenge in analog circuit design is that all salient design metrics such as power, area, bandwidth and accuracy are interrelated. Furthermore, poor flexibility, i.e. lack of reconfigurability, the reuse of IP etc., can be considered the most severe weakness of analog hardware. On this account, digital calibration schemes are often required for improved performance or yield enhancement, whereas high flexibility/reconfigurability can not be easily achieved. Here, it is discussed whether it is possible to work around these obstacles by using floating-gate transistors (FGTs), and analyze problems associated with the practical implementation. FGT technology is attractive because it is electrically programmable and also features a charge-based built-in non-volatile memory. Apart from being ideal for canceling the circuit non-idealities due to process variations, the FGTs can also be used as computational or adaptive elements in analog circuits. The nominal gate oxide thickness in the deep sub-micron (DSM) processes is too thin to support robust charge retention and consequently the FGT becomes leaky. In principle, non-leaky FGTs can be implemented in a scaled down process without any special masks by using “double”-oxide transistors intended for providing devices that operate with higher supply voltages than general purpose devices. However, in practice the technology scaling poses several challenges which are addressed in this thesis. To provide a sufficiently wide-ranging survey, six prototype chips with varying complexity were implemented in four different DSM process nodes and investigated from this perspective. The focus is on non-leaky FGTs, but the presented autozeroing floating-gate amplifier (AFGA) demonstrates that leaky FGTs may also find a use. The simplest test structures contain only a few transistors, whereas the most complex experimental chip is an implementation of a spiking neural network (SNN) which comprises thousands of active and passive devices. More precisely, it is a fully connected (256 FGT synapses) two-layer spiking neural network (SNN), where the adaptive properties of FGT are taken advantage of. A compact realization of Spike Timing Dependent Plasticity (STDP) within the SNN is one of the key contributions of this thesis. Finally, the considerations in this thesis extend beyond CMOS to emerging nanodevices. To this end, one promising emerging nanoscale circuit element - memristor - is reviewed and its applicability for analog processing is considered. Furthermore, it is discussed how the FGT technology can be used to prototype computation paradigms compatible with these emerging two-terminal nanoscale devices in a mature and widely available CMOS technology.

Microsoftin pilvipalvelut pk-yrityksen päätelaite- ja tiedonhallinnassa

Diplomityössä tutkittiin Microsoftin pilvipalveluiden käyttöä pk-yrityksen päätelaitteiden hallinnassa sekä yrityksen tiedonhallinnassa. Kohdeyrityksenä oli pk-yritys, jolla on ollut Microsoftin pilvipalveluita käytössä jo useamman vuoden ajan. Pilvipalveluiden nopean päivitystahdin myötä uusimpien ominaisuuksien hyödyntäminen on suurelta osin jäänyt tekemättä. Tutkimus päädyttiin rajaamaan kohdeyrityksessä tehdyn vaatimusmäärittelyn mukaisiin tapauksiin, joihin pyrittiin etsimään vastauksia Microsoftin pilvipalveluiden tämän hetken ominaisuuksien avulla. Tutkimus toteutettiin tutustumalla kirjallisuuden avulla pilvitoimintamallin perusteisiin ja Microsoftin tarjoamiin pilvipalveluihin. Työn käytännön osuus toteutettiin useilla eri päätelaitteilla Office 365:den ja Windows Intunen muodostamassa testiympäristössä, jota laajennettiin Microsoft Azuren mahdollistamilla lisäominaisuuksilla. Pilvitoimintamallin yritykset taistelevat jatkuvasti käyttäjien luottamuksesta ja NSA:n vakoilutapauksen jälkeen palveluissa on tapahtunut paljon parannuksia. Tutkimuksessa todettiin erityisesti tiedon suojaamiskäytäntöjen ja hallintaominaisuuksien kehittyneen viime vuosina pilvitoimintamallin yritysten keskinäisen kilpailun myötä. Microsoftin pilvipalvelujen uudet ominaisuudet tarjoavat pk-yritysten käyttöön tehokkaita päätelaite- ja tiedonhallintaratkaisuja, joita on tähän asti ollut saatavilla vain suuryritysympäristöissä.

Virtual Runtime Application Partitions for Resource Management in Massively Parallel Architectures

This thesis presents a novel design paradigm, called Virtual Runtime Application Partitions (VRAP), to judiciously utilize the on-chip resources. As the dark silicon era approaches, where the power considerations will allow only a fraction chip to be powered on, judicious resource management will become a key consideration in future designs. Most of the works on resource management treat only the physical components (i.e. computation, communication, and memory blocks) as resources and manipulate the component to application mapping to optimize various parameters (e.g. energy efficiency). To further enhance the optimization potential, in addition to the physical resources we propose to manipulate abstract resources (i.e. voltage/frequency operating point, the fault-tolerance strength, the degree of parallelism, and the configuration architecture). The proposed framework (i.e. VRAP) encapsulates methods, algorithms, and hardware blocks to provide each application with the abstract resources tailored to its needs. To test the efficacy of this concept, we have developed three distinct self adaptive environments: (i) Private Operating Environment (POE), (ii) Private Reliability Environment (PRE), and (iii) Private Configuration Environment (PCE) that collectively ensure that each application meets its deadlines using minimal platform resources. In this work several novel architectural enhancements, algorithms and policies are presented to realize the virtual runtime application partitions efficiently. Considering the future design trends, we have chosen Coarse Grained Reconfigurable Architectures (CGRAs) and Network on Chips (NoCs) to test the feasibility of our approach. Specifically, we have chosen Dynamically Reconfigurable Resource Array (DRRA) and McNoC as the representative CGRA and NoC platforms. The proposed techniques are compared and evaluated using a variety of quantitative experiments. Synthesis and simulation results demonstrate VRAP significantly enhances the energy and power efficiency compared to state of the art.

Modeling Front End Electronics for a Gas Electron Multiplier Detector

The Large Hadron Collider (LHC) in The European Organization for Nuclear Research (CERN) will have a Long Shutdown sometime during 2017 or 2018. During this time there will be maintenance and a possibility to install new detectors. After the shutdown the LHC will have a higher luminosity. A promising new type of detector for this high luminosity phase is a Triple-GEM detector. During the shutdown these detectors will be installed at the Compact Muon Solenoid (CMS) experiment. The Triple-GEM detectors are now being developed at CERN and alongside also a readout ASIC chip for the detector. In this thesis a simulation model was developed for the ASICs analog front end. The model will help to carry out more extensive simulations and also simulate the whole chip before the whole design is finished. The proper functioning of the model was tested with simulations, which are also presented in the thesis.

Local Binary Patterns in Focal-Plane Processing. Analysis and Applications

Feature extraction is the part of pattern recognition, where the sensor data is transformed into a more suitable form for the machine to interpret. The purpose of this step is also to reduce the amount of information passed to the next stages of the system, and to preserve the essential information in the view of discriminating the data into different classes. For instance, in the case of image analysis the actual image intensities are vulnerable to various environmental effects, such as lighting changes and the feature extraction can be used as means for detecting features, which are invariant to certain types of illumination changes. Finally, classification tries to make decisions based on the previously transformed data. The main focus of this thesis is on developing new methods for the embedded feature extraction based on local non-parametric image descriptors. Also, feature analysis is carried out for the selected image features. Low-level Local Binary Pattern (LBP) based features are in a main role in the analysis. In the embedded domain, the pattern recognition system must usually meet strict performance constraints, such as high speed, compact size and low power consumption. The characteristics of the final system can be seen as a trade-off between these metrics, which is largely affected by the decisions made during the implementation phase. The implementation alternatives of the LBP based feature extraction are explored in the embedded domain in the context of focal-plane vision processors. In particular, the thesis demonstrates the LBP extraction with MIPA4k massively parallel focal-plane processor IC. Also higher level processing is incorporated to this framework, by means of a framework for implementing a single chip face recognition system. Furthermore, a new method for determining optical flow based on LBPs, designed in particular to the embedded domain is presented. Inspired by some of the principles observed through the feature analysis of the Local Binary Patterns, an extension to the well known non-parametric rank transform is proposed, and its performance is evaluated in face recognition experiments with a standard dataset. Finally, an a priori model where the LBPs are seen as combinations of n-tuples is also presented