Tulosyksikkölaskentamallin kehittäminen teollisuusyrityksen ohjauksen välineeksi

Tämän diplomityön kohdeyrityksenä toimii prosessijohtamismallin mukaisesti organisoitunut sellua valmistava ja toimittava yritys. Yritys valmistaa omaa sellua neljällä tehtaalla, jotka sijaitsevat eri paikkakunnilla. Tulosyksikkölaskentaa kehittämällä yritys haluaa tuoda esiin tehtaiden oman toiminnan merkityksen myös prosessijohtamisen toimintamallia noudatettaessa ja saada selville tehtaiden todellisen suorituksen tason. Tutkimusotteeltaan työ on konstruktiivinen, mutta siinä voidaan havaita piirteitä myös toiminta-analyyttisesta tutkimusotteesta. Työn tavoitteena oli kehittää kohdeyrityksen käyttöön yksinkertainen, selkeä ja helppokäyttöinen laskentamalli, jonka avulla yrityksen on mahdollista tarkastella ja vertailla eri tehtaiden tuotantoprosessien toiminnan tehokkuutta sekä sen kehitystä. Mallin rakentaminen perustui ohjattavuuden periaatteeseen pohjautuvaan vastuualuelaskentaan. Lisäksi mallin kehittämisessä hyödynnettiin benchmarkingin ja kapasiteettitarkastelun ajatuksia. Mallintamisen lähtökohtia selvitettiin kohdeyrityksen henkilöstön kanssa suoritettujen teemahaastattelujen avulla. Työn merkittävimpänä tuloksena syntyi teoreettisen aineiston, haastatteluihin perustuvan kvalitatiivisen tiedon sekä yrityksen tietojärjestelmistä saatavan datan avulla luotu laskentamalli. Mallin toimintaa tarkasteltiin sijoittamalla malliin tietyltä ajanjaksolta kerättyä numeerista aineistoa. Mallin avulla yrityksen on mahdollista aiempaa paremmin tarkastella eri tehtaiden onnistumista tuotantotoiminnassaan. Mallissa korostettiin, että tehtaiden on pystyttävä hallitsemaan omat erityispiirteensä, minkä vuoksi mallin antamia tuloksia tarkasteltaessa on huomioitava myös mahdolliset mallintamisen taustalla vaikuttavat tekijät. Mallintamisen lopputuloksena syntynyt selkeä perusmalli luo hyvät lähtökohdat myös mahdolliselle jatkokehitykselle.

Active inverter output filtering methods

Frequency converters are widely used in the industry to enable better controllability and efficiency of variable speed AC motor drives. Despite these advantages, certain challenges concerning the inverter and motor interfacing have been present for decades. As insulated gate bipolar transistors entered the market, the inverter output voltage transition rate significantly increased compared with their predecessors. Inverters operate based on pulse width modulation of the output voltage, and the steep voltage edge fed by the inverter produces a motor terminal overvoltage. The overvoltage causes extra stress to the motor insulation, which may lead to a prematuremotor failure. The overvoltage is not generated by the inverter alone, but also by the sum effect of the motor cable length and the impedance mismatch between the cable and the motor. Many solutions have been shown to limit the overvoltage, and the mainstream products focus on passive filters. This doctoral thesis studies an alternative methodology for motor overvoltage reduction. The focus is on minimization of the passive filter dimensions, physical and electrical, or better yet, on operation without any filter. This is achieved by additional inverter control and modulation. The studied methods are implemented on different inverter topologies, varying in nominal voltage and current.For two-level inverters, the studied method is termed active du/dt. It consists of a small output LC filter, which is controlled by an independent modulator. The overvoltage is limited by a reduced voltage transition rate. For multilevel inverters, an overvoltage mitigation method operating without a passive filter, called edge modulation, is implemented. The method uses the capability of the inverter to produce two switching operations in the same direction to cancel the oscillating voltages of opposite phases. For parallel inverters, two methods are studied. They are both intended for two-level inverters, but the first uses individual motor cables from each inverter while the other topology applies output inductors. The overvoltage is reduced by interleaving the switching operations to produce a similar oscillation accumulation as with the edge modulation. The implementation of these methods is discussed in detail, and the necessary modifications to the control system of the inverter are presented. Each method is experimentally verified by operating industrial frequency converters with the modified control. All the methods are found feasible, and they provide sufficient overvoltage protection. The limitations and challenges brought about by the methods are discussed.

On Dynamic Monitoring Methods for Networks-on-Chip

Rapid ongoing evolution of multiprocessors will lead to systems with hundreds of processing cores integrated in a single chip. An emerging challenge is the implementation of reliable and efficient interconnection between these cores as well as other components in the systems. Network-on-Chip is an interconnection approach which is intended to solve the performance bottleneck caused by traditional, poorly scalable communication structures such as buses. However, a large on-chip network involves issues related to congestion problems and system control, for instance. Additionally, faults can cause problems in multiprocessor systems. These faults can be transient faults, permanent manufacturing faults, or they can appear due to aging. To solve the emerging traffic management, controllability issues and to maintain system operation regardless of faults a monitoring system is needed. The monitoring system should be dynamically applicable to various purposes and it should fully cover the system under observation. In a large multiprocessor the distances between components can be relatively long. Therefore, the system should be designed so that the amount of energy-inefficient long-distance communication is minimized. This thesis presents a dynamically clustered distributed monitoring structure. The monitoring is distributed so that no centralized control is required for basic tasks such as traffic management and task mapping. To enable extensive analysis of different Network-on-Chip architectures, an in-house SystemC based simulation environment was implemented. It allows transaction level analysis without time consuming circuit level implementations during early design phases of novel architectures and features. The presented analysis shows that the dynamically clustered monitoring structure can be efficiently utilized for traffic management in faulty and congested Network-on-Chip-based multiprocessor systems. The monitoring structure can be also successfully applied for task mapping purposes. Furthermore, the analysis shows that the presented in-house simulation environment is flexible and practical tool for extensive Network-on-Chip architecture analysis.