Towards a user-friendly webservice architecture for statistical machine translation in the PANACEA project

This paper presents a webservice architecture for Statistical Machine Translation aimed at non-technical users. A workfloweditor allows a user to combine different webservices using a graphical user interface. In the current state of this project,the webservices have been implemented for a range of sentential and sub-sententialaligners. The advantage of a common interface and a common data format allows the user to build workflows exchanging different aligners.

Adaptive integral assessment package for the A2UN@ project

This paper presents a first approach of Evaluation Engine Architecture (EEA) as proposal to support adaptive integral assessment, in the context of a virtual learning environment. The goal of our research is design an evaluation engine tool to assist in the whole assessment process within the A2UN@ project, linking that tool with the other key elements of a learning design (learning task, learning resources and learning support). The teachers would define the relation between knowledge, competencies, activities, resources and type of assessment. Providing this relation is possible obtain more accurate estimations of student's knowledge for adaptive evaluations and future recommendations. The process is supported by usage of educational standards and specifications and for an integral user modelling

Reconfigurable Architecture To Estimate The Motion Of An Underwater Vehicle

This work proposes a parallel architecture for a motion estimation algorithm. It is well known that image processing requires a huge amount of computation, mainly at low level processing where the algorithms are dealing with a great numbers of data-pixel. One of the solutions to estimate motions involves detection of the correspondences between two images. Due to its regular processing scheme, parallel implementation of correspondence problem can be an adequate approach to reduce the computation time. This work introduces parallel and real-time implementation of such low-level tasks to be carried out from the moment that the current image is acquired by the camera until the pairs of point-matchings are detected

A design for an advanced architecture of satellite ground segments

This project proposes a preliminary architectural design for a control and data processing center, also known as 'ground segment', for Earth observation satellites.

The Catalan countries project (1931-1939)

In the evolution of Catalan nationalism, as much politician as cultural, the period of II Spanish Republic (1931-1939) was essential. The obtaining of the Statute of Autonomy (1931-1932) supposed the beginning of a stage of expansion in multiple aspects. One of them were the contacts with the Catalanists nuclei of the rest of the cultural space of Catalan language in which, at that time, it would begin to call Catalan Countries (Balearic Islands, Valencian Country, Andorra, Rosselló, to l'Alguer). On Those Collaborations between cultural organizations, political and particular parties Catalonia always will be the model to follow. The Increasing connections will be visualized on press, as well as on cultural celebrations, policy of parties and Constituent Courts. This evolution will be cut by the Franco victory in the Civil War in 1939.

Transferring QTL technology to the pig breeding industry (PigQTech) - a demonstration project

The aim of the project has been to demonstrate how the farm animal breeding industry can utilise gene mapping technology to accelerate genetic improvement. Previous theoretical studies had suggested that the use of marker assisted selection could potentially increase the annual improvement for quantitative traits like backfat with about 10% and for more difficult traits such as meat quality and reproduction by as much as 40-60% compared with existing technology. The work has comprised two major tasks: 1. Commercially relevant populations have been screened for segregation at QTLs identified in experimental populations. The aim has been to establish optimal strategies for QTL detection in commercial pig populations and the extent to which QTLs explaining major phenotypic differences between divergent lines used in experimental studies also explain quantitative variation within commercial lines. The results are important for specifying future strategies for finding economically valuable QTLs. 2. Marker assisted backcrossing has been used to demonstrate how a QTL allele can be introgressed from one breed to another. The work has focused on the major fatness QTL on pig chromosome 4 previously identified in a wild pig/Large White intercross. The end result was not designed to be a commercially viable product in its own right, but the process has validated a number of points of major importance for the exploitation of QTLs in livestock.

Mobilitat inter-plataforma d'agents software: protocol de migració fragmentada

En aquest projecte s'ha realitzat l'anàlisi, disseny i implementació d'un protocol de migració d'agents software basat en l'enviament del codi dels agents fragmentat en múltiples missatges. Aquest protocol es troba dins d'una arquitectura de migració multi-protocol per a la mobilitat d'agents entre plataformes JADE. Finalment, s'ha realitzat un estudi que compara el rendiment assolit pel protocol i les prestacions que aporta.

Análisis y diseño de un procesador RISC simple para adquisición y proceso de datos

Aquest projecte té com a objectiu l'anàlisi de prestacions de processadors RISC de baix cost i el disseny d'un processador RISC simple per a aplicacions de propòsit general relacionades amb l'adquisició i el procés simple de dades. Com a resultat es presenta el processador SR3C de 32 bits i arquitectura RISC. Aquest processador s'ha descrit i simulat mitjançant el llenguatge de descripció de hardware VHDL i s'ha sintetitzat en una FPGA. El processador està preparat per poder utilitzar-se en SoCs reals gràcies al compliment de l'estàndard de busos Wishbone. A més també es pot utilitzar com plataforma educativa gràcies a l'essamblador i simulador desenvolupats.

Sistema gràfic de depuració per xarxes (NoC)

Aquest projecte descriu el disseny i desenvolupament d’una eina gràfica per a la depuració de projectes desenvolupats amb un llenguatge de descripció de sistemes com és el SystemC. Amb aquest llenguatge s’ha desenvolupat una NoC (Network on Chip). L’eina desenvolupada mostra de forma visual l’arquitectura de la xarxa NoC, els valors dels senyals que es transmeten a través de la xarxa i estadístiques sobre aquests per tal de poder fer un seguiment exhaustiu i agilitzar la recerca d’errors com interbloquejos, pèrdua de dades i d’altres. Al concentrar en un únic entorn la descripció de la NoC i les dades relatives a les senyals en temps de simulació, proporciona un valor afegit a altres eines disponibles per a realitzar aquesta tasca.

Simulació d'arquitectures VLIW

L'objectiu d'aquest projecte es dissenyar i implementar en Java una interfície gràfica que permeti simular l'arquitectura VLIW. Ha d'interactuar amb un simulador ja existent, VEX, i amb l'usuari. VEX permet analitzar, desenvolupar i depurar codi escrit en C sobre un processador VLIW configurable, des dels recursos hardware fíns al comportament de la "caché". L'interfície gràfica desenvolupada es diu JavaVEX. Té el gran avantatge d'evitar la introducció de les comandes de text que necesita VEX perquè son substituïdes per elements. És una eina més intuïtiva, ràpida i eficient. JavaVEX mostra informació sobre el codi C traduït a instruccions VLIW de fins a 4 operacions. També mostra els resultats de les instrucciones VLIW simulades. JavaVEX s'ha incorporat a un LiveCD. Així es pot executar l'aplicació sobre qualsevol ordinador. La finalitat docent de JavaVEX és ser utilitzada en les pràctiques de l'assignatura Arquitectura per a Computadors 2.

Arquitectura wormhole per a una NoC 2D-Mesh

Aquest projecte presenta la implementació d'un disseny, i la seva posterior síntesi en una FPGA, d'una arquitectura de tipus wormhole packet switching per a una infraestructura de NetWork-On-Chip amb una topologia 2D-Mesh. Agafant un router circuit switching com a punt de partida, s'han especificat els mòduls en Verilog per tal d'obtenir l'arquitectura wormhole desitjada. Dissenyar la màquina de control per governar els flits que conformen els paquets dins la NoC,i afegir les cues a la sortida del router (outuput queuing) són els punts principals d'aquest treball. A més, com a punt final s'han comparat ambdues arquitectures de router en termes de costos en àrea i en memòria i se n’han obtingut diverses conclusions i resultats experimentals.

Inequality and a repeated joint project

Agents voluntarily contribute to an infinitely repeated joint project. We investigate the conditions for cooperation to be a renegotiation-proof and coalition-proof equilibrium before examining the influence of output share inequality on the sustainability of cooperation. When shares are not equally distributed, cooperation requires agents to be more patient than under perfect equality. Beyond a certain degree of share inequality, full efficiency cannot be reached without redistribution. This model also explains the coexistence of one cooperating and one free-riding coalition. In this case, increasing inequality can have a positive or negative impact on the aggregate level of effort.

Label Space Reduction in All-Optical Label Switchiing Networks

Report for the scientific sojourn at the Department of Information Technology (INTEC) at the Ghent University, Belgium, from january to june 2007. All-Optical Label Swapping (AOLS) forms a key technology towards the implementation of All-Optical Packet Switching nodes (AOPS) for the future optical Internet. The capital expenditures of the deployment of AOLS increases with the size of the label spaces (i.e. the number of used labels), since a special optical device is needed for each recognized label on every node. Label space sizes are affected by the wayin which demands are routed. For instance, while shortest-path routing leads to the usage of fewer labels but high link utilization, minimum interference routing leads to the opposite. This project studies and proposes All-Optical Label Stacking (AOLStack), which is an extension of the AOLS architecture. AOLStack aims at reducing label spaces while easing the compromise with link utilization. In this project, an Integer Lineal Program is proposed with the objective of analyzing the softening of the aforementioned trade-off due to AOLStack. Furthermore, a heuristic aiming at finding good solutions in polynomial-time is proposed as well. Simulation results show that AOLStack either a) reduces the label spaces with a low increase in the link utilization or, similarly, b) uses better the residual bandwidth to decrease the number of labels even more.

RADIC II: a fault tolerant architecture with flexible dynamic redundancy

The demand for computational power has been leading the improvement of the High Performance Computing (HPC) area, generally represented by the use of distributed systems like clusters of computers running parallel applications. In this area, fault tolerance plays an important role in order to provide high availability isolating the application from the faults effects. Performance and availability form an undissociable binomial for some kind of applications. Therefore, the fault tolerant solutions must take into consideration these two constraints when it has been designed. In this dissertation, we present a few side-effects that some fault tolerant solutions may presents when recovering a failed process. These effects may causes degradation of the system, affecting mainly the overall performance and availability. We introduce RADIC-II, a fault tolerant architecture for message passing based on RADIC (Redundant Array of Distributed Independent Fault Tolerance Controllers) architecture. RADIC-II keeps as maximum as possible the RADIC features of transparency, decentralization, flexibility and scalability, incorporating a flexible dynamic redundancy feature, allowing to mitigate or to avoid some recovery side-effects.

System analysis of a Peer-to-Peer Video-on-Demand architecture: Kangaroo

Architectural design and deployment of Peer-to-Peer Video-on-Demand (P2PVoD) systems which support VCR functionalities is attracting the interest of an increasing number of research groups within the scientific community; especially due to the intrinsic characteristics of such systems and the benefits that peers could provide at reducing the server load. This work focuses on the performance analysis of a P2P-VoD system considering user behaviors obtained from real traces together with other synthetic user patterns. The experiments performed show that it is feasible to achieve a performance close to the best possible. Future work will consider monitoring the physical characteristics of the network in order to improve the design of different aspects of a VoD system.