Development of laser-fired contacts for amorphous silicon layers obtained by Hot-Wire CVD

In this work we study aluminium laser-fired contacts for intrinsic amorphous silicon layers deposited by Hot-Wire CVD. This structure could be used as an alternative low temperature back contact for rear passivated heterojunction solar cells. An infrared Nd:YAG laser (1064 nm) has been used to locally fire the aluminium through the thin amorphous silicon layers. Under optimized laser firing parameters, very low specific contact resistances (ρc ∼ 10 mΩ cm2) have been obtained on 2.8 Ω cm p-type c-Si wafers. This investigation focuses on maintaining the passivation quality of the interface without an excessive increase in the series resistance of the device.

Uniformity Study of Amorphous and Microcrystalline Silicon Thin Films Deposited on 10cmx10cm Glass Substrate using Hot Wire CVD Technique

The scaling up of the Hot Wire Chemical Vapor Deposition (HW-CVD) technique to large deposition area can be done using a catalytic net of equal spaced parallel filaments. The large area deposition limit is defined as the limit whenever a further increment of the catalytic net area does not affect the properties of the deposited film. This is the case when a dense catalytic net is spread on a surface considerably larger than that of the film substrate. To study this limit, a system able to hold a net of twelve wires covering a surface of about 20 cm x 20 cm was used to deposit amorphous (a-Si:H) and microcrystalline (μc-Si:H) silicon over a substrate of 10 cm x 10 cm placed at a filament-substrate distance ranging from 1 to 2 cm. The uniformity of the film thickness d and optical constants, n(x, λ) and α(x,¯hω), was studied via transmission measurements. The thin film uniformity as a function of the filament-substrate distance was studied. The experimental thickness profile was compared with the theoretical result obtained solving the diffusion equations. The optimization of the filament-substrate distance allowed obtaining films with inhomogeneities lower than ±2.5% and deposition rates higher than 1 nm/s and 4.5 nm/s for (μc-Si:H) and (a-Si:H), respectively.

Low temperature amorphous and nanocrystalline silicon thin film transistors deposited by Hot-Wire CVD on glass substrate

Amorphous and nanocrystalline silicon films obtained by Hot-Wire Chemical Vapor Deposition have been incorporated as active layers in n-type coplanar top gate thin film transistors deposited on glass substrates covered with SiO 2. Amorphous silicon devices exhibited mobility values of 1.3 cm 2 V - 1 s - 1, which are very high taking into account the amorphous nature of the material. Nanocrystalline transistors presented mobility values as high as 11.5 cm 2 V - 1 s - 1 and resulted in low threshold voltage shift (∼ 0.5 V).

Substrate influence on the properties of doped thin silicon layers grown by Cat-CVD

We present structural and electrical properties for p- and n-type layers grown close to the transition between a-Si:H and nc-Si:H onto different substrates: Corning 1737 glass, ZnO:Al-coated glass and stainless steel. Structural properties were observed to depend on the substrate properties for samples grown under the same deposition conditions. Different behaviour was observed for n- and p-type material. Stainless steel seemed to enhance crystallinity when dealing with n-type layers, whereas an increased crystalline fraction was obtained on glass for p-type samples. Electrical conduction in the direction perpendicular to the substrate seemed to be mainly determined by the interfaces or by the existence of an amorphous incubation layer that might determine the electrical behaviour. In the direction perpendicular to the substrate, n-type layers exhibited a lower resistance value than p-type ones, showing better contact properties between the layer and the substrate.

Optimisation of doped microcrystalline silicon films deposited at very low temperatures by Hot-Wire CVD

In this paper we present new results on doped μc-Si:H thin films deposited by hot-wire chemical vapour deposition (HWCVD) in the very low temperature range (125-275°C). The doped layers were obtained by the addition of diborane or phosphine in the gas phase during deposition. The incorporation of boron and phosphorus in the films and their influence on the crystalline fraction are studied by secondary ion mass spectrometry and Raman spectroscopy, respectively. Good electrical transport properties were obtained in this deposition regime, with best dark conductivities of 2.6 and 9.8 S cm -1 for the p- and n-doped films, respectively. The effect of the hydrogen dilution and the layer thickness on the electrical properties are also studied. Some technological conclusions referred to cross contamination could be deduced from the nominally undoped samples obtained in the same chamber after p- and n-type heavily doped layers.

Study of post-deposition contamination in low-temperature deposited polysilicon films

The presence of hydrogen in polysilicon films obtained at low temperatures by hot-wire CVD and the post-deposition oxidation by air-exposure of the films are studied in this paper. The experimental results from several characterization techniques (infrared spectroscopy, X-ray photoelectron spectroscopy, secondary ion mass spectrometry and wavelength dispersive spectroscopy) showed that hydrogen and oxygen are homogeneously distributed at grain boundaries throughout the depth of the films. Hydrogen is introduced during the growth process and its concentration is higher in samples deposited at lower temperatures. Oxygen diffuses along the grain boundaries and binds to silicon atoms, mainly in Si 2O groups.

Progress in a-Si:H/c-Si heterojunction emitters obtained by Hot-Wire CVD at 200°C

In this work, we investigate heterojunction emitters deposited by Hot-Wire CVD on p-type crystalline silicon. The emitter structure consists of an n-doped film (20 nm) combined with a thin intrinsic hydrogenated amorphous silicon buffer layer (5 nm). The microstructure of these films has been studied by spectroscopic ellipsometry in the UV-visible range. These measurements reveal that the microstructure of the n-doped film is strongly influenced by the amorphous silicon buffer. The Quasy-Steady-State Photoconductance (QSS-PC) technique allows us to estimate implicit open-circuit voltages near 700 mV for heterojunction emitters on p-type (0.8 Ω·cm) FZ silicon wafers. Finally, 1 cm 2 heterojunction solar cells with 15.4% conversion efficiencies (total area) have been fabricated on flat p-type (14 Ω·cm) CZ silicon wafers with aluminum back-surface-field contact.

Investigation of defect formation and electronic transport in microcrystalline silicon deposited by hot-wire CVD

We have investigated doped and undoped layers of microcrystalline silicon prepared by hot-wire chemical vapour deposition optically, electrically and by means of transmission electron microscopy. Besides needle-like crystals grown perpendicular to the substrate's surface, all of the layers contained a noncrystalline phase with a volume fraction between 4% and 25%. A high oxygen content of several per cent in the porous phase was detected by electron energy loss spectrometry. Deep-level transient spectroscopy of the crystals suggests that the concentration of electrically active defects is less than 1% of the undoped background concentration of typically 10^17 cm -3. Frequency-dependent measurements of the conductance and capacitance perpendicular to the substrate surface showed that a hopping process takes place within the noncrystalline phase parallel to the conduction in the crystals. The parasitic contribution to the electrical circuit arising from the porous phase is believed to be an important loss mechanism in the output of a pin-structured photovoltaic solar cell deposited by hot-wire CVD.

Studies on grain boundaries in nanocrystalline silicon grown by Hot-Wire CVD

The use of a tantalum wire in hot-wire chemical vapour deposition (HWCVD) has allowed the deposition of dense nanocrystalline silicon at low filament temperatures (1550 °C). A transition in the crystalline preferential orientation from (2 2 0) to (1 1 1) was observed around 1700 °C. Transmission electron microscopy (TEM) images, together with secondary ion mass spectrometry (SIMS) measurements, suggested that no oxidation occurred in materials obtained at low filament temperature due to the high density of the tissue surrounding grain boundaries. A greater concentration of SiH 3 radicals formed at these temperatures seemed to be responsible for the higher density.

Hot wire configuration for depositing device grade nano-crystalline silicon at high deposition rate

The University of Barcelona is developing a pilot-scale hot wire chemical vapor deposition (HW-CVD) set up for the deposition of nano-crystalline silicon (nc-Si:H) on 10 cm × 10 cm glass substrate at high deposition rate. The system manages 12 thin wires of 0.15-0.2 mm diameter in a very dense configuration. This permits depositing very uniform films, with inhomogeneities lower than 2.5%, at high deposition rate (1.5-3 nm/s), and maintaining the substrate temperature relatively low (250 °C). The wire configuration design, based on radicals' diffusion simulation, is exposed and the predicted homogeneity is validated with optical transmission scanning measurements of the deposited samples. Different deposition series were carried out by varying the substrate temperature, the silane to hydrogen dilution and the deposition pressure. By means of Fourier transform infrared spectroscopy (FTIR), the evolution in time of the nc-Si:H vibrational modes was monitored. Particular importance has been given to the study of the material stability against post-deposition oxidation.

Progress in single junction microcrystalline silicon solar cells deposited by Hot-Wire CVD

Hot-Wire Chemical Vapor Deposition has led to microcrystalline silicon solar cell efficiencies similar to those obtained with Plasma Enhanced CVD. The light-induced degradation behavior of microcrystalline silicon solar cells critically depends on the properties of their active layer. In the regime close to the transition to amorphous growth (around 60% of amorphous volume fraction), cells incorporating an intrinsic layer with slightly higher crystalline fraction and [220] preferential orientation are stable after more than 7000 h of AM1.5 light soaking. On the contrary, solar cells whose intrinsic layer has a slightly lower crystalline fraction and random or [111] preferential orientation exhibit clear light-induced degradation effects. A revision of the efficiencies of Hot-Wire deposited microcrystalline silicon solar cells is presented and the potential efficiency of this technology is also evaluated.

Surface passivation of crystalline silicon by Cat-CVD amorphous and nanocrystalline thin silicon films

In this work, we study the electronic surface passivation of crystalline silicon with intrinsic thin silicon films deposited by Catalytic CVD. The contactless method used to determine the effective surface recombination velocity was the quasi-steady-state photoconductance technique. Hydrogenated amorphous and nanocrystalline silicon films were evaluated as passivating layers on n- and p-type float zone silicon wafers. The best results were obtained with amorphous silicon films, which allowed effective surface recombination velocities as low as 60 and 130 cms -1 on p- and n-type silicon, respectively. To our knowledge, these are the best results ever reported with intrinsic amorphous silicon films deposited by Catalytic CVD. The passivating properties of nanocrystalline silicon films strongly depended on the deposition conditions, especially on the filament temperature. Samples grown at lower filament temperatures (1600 °C) allowed effective surface recombination velocities of 450 and 600 cms -1 on n- and p-type silicon.

Electronic transport in low temperature nanocrystalline silicon thin-film transistors obtained by Hot-Wire CVD

Hydrogenated nanocrystalline silicon (nc-Si:H) obtained by hot-wire chemical vapour deposition (HWCVD) at low substrate temperature (150 °C) has been incorporated as the active layer in bottom-gate thin-film transistors (TFTs). These devices were electrically characterised by measuring in vacuum the output and transfer characteristics for different temperatures. The field-effect mobility showed a thermally activated behaviour which could be attributed to carrier trapping at the band tails, as in hydrogenated amorphous silicon (a-Si:H), and potential barriers for the electronic transport. Trapped charge at the interfaces of the columns, which are typical in nc-Si:H, would account for these barriers. By using the Levinson technique, the quality of the material at the column boundaries could be studied. Finally, these results were interpreted according to the particular microstructure of nc-Si:H.

Microcrystalline silicon thin film transistors obtained by Hot-Wire CVD

Polysilicon thin film transistors (TFT) are of great interest in the field of large area microelectronics, especially because of their application as active elements in flat panel displays. Different deposition techniques are in tough competition with the objective to obtain device-quality polysilicon thin films at low temperature. In this paper we present the preliminary results obtained with the fabrication of TFT deposited by hot-wire chemical vapor deposition (HWCVD). Some results concerned with the structural characterization of the material and electrical performance of the device are presented.

Thin Film Transistors obtained by Hot-Wire CVD

Hydrogenated microcrystalline silicon films obtained at low temperature (150-280°C) by hot wire chemical vapour deposition at two different process pressures were measured by Raman spectroscopy, X-ray diffraction (XRD) spectroscopy and photothermal deflection spectroscopy (PDS). A crystalline fraction >90% with a subgap optical absortion 10 cm -1 at 0.8 eV were obtained in films deposited at growth rates >0.8 nm/s. These films were incorporated in n-channel thin film transistors and their electrical properties were measured. The saturation mobility was 0.72 ± 0.05 cm 2/ V s and the threshold voltage around 0.2 eV. The dependence of their conductance activation energies on gate voltages were related to the properties of the material.