31 resultados para bilayer gate dielectric
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Applied Physics Letters, Vol.93, issue 20
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IEEE Electron Device Letters, VOL. 29, NO. 9,
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Dissertação para obtenção do grau de mestre em Engenharia de Materiais
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Digital microfluidics (DMF) is a field which has emerged in the last decade as a re-liable and versatile tool for sensing applications based on liquid reactions. DMF allows the discrete displacement of droplets, over an array of electrodes, by the application of voltage, and also the dispensing from a reservoir, mixing, merging and splitting fluidic operations. The main drawback of these devices is due to the need of high driving volt-ages for droplet operations. In this work, alternative dielectric layers combinations were studied aiming the reduction of these driving voltages. DMF chips were designed, pro-duced and optimized according to the theory of electrowetting-on-dielectric, adopting different combinations of parylene-C and tantalum pentoxide (Ta2O5) as dielectric ma-terials, and Teflon as hydrophobic layer. With both devices’ configurations, i.e., Parylene as single dielectric, and multilayer chips combining Parylene and Ta2O5, it was possible to perform all the fluidic opera-tions in the microliter down to hundreds of nanoliters range. Multilayer chips presented significant reduction on driving voltages for droplet op-erations in silicone oil filler medium: from 70 V (parylene only) down to 30 V (parylene/Ta2O5) for dispensing; and from 50 V (parylene only) down to 15 V (parylene/Ta2O5) for movement. Peroxidase colorimetric reactions were successfully performed as proof-of-concept, using multilayer configuration devices.
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This work reports the development of field-effect transistors (FETs), whose channel is based on zinc oxide (ZnO) nanoparticles (NPs). Using screen-printing as the primary deposition technique, different inks were developed, where the semiconducting ink is based on a ZnO NPs dispersion in ethyl cellulose (EC). These inks were used to print electrolyte-gated transistors (EGTs) in a staggered-top gate structure on glass substrates, using a lithium-based polymeric electrolyte. In another approach, FETs with a staggered-bottom gate structure on paper were developed using a sol-gel method to functionalize the paper’s surface with ZnO NPs, using zinc acetate dihydrate (ZnC4H6O4·2H2O) and sodium hydroxide (NaOH) as precursors. In this case, the paper itself was used as dielectric. The various layers of the two devices were characterized using X-ray diffraction (XRD), scanning electron microscopy (SEM), Fourier Transform Infrared spectroscopy (FTIR), thermogravimetric and differential scanning calorimetric analyses (TG-DSC). Electrochemical impedance spectroscopy (EIS) was used in order to evaluate the electric double-layer (EDL) formation, in the case of the EGTs. The ZnO NPs EGTs present electrical modulation for annealing temperatures equal or superior to 300 ºC and in terms of electrical properties they showed On/Off ratios in the order of 103, saturation mobilities (μSat) of 1.49x10-1 cm2(Vs)-1 and transconductance (gm) of 10-5 S. On the other hand, the ZnO NPs FETs on paper exhibited On/Off ratios in the order of 102, μSat of 4.83x10- 3 cm2(Vs)-1and gm around 10-8 S.
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This work will discuss the use of different paper membranes as both the substrate and dielectric for field-effect memory transistors. Three different nanofibrillated cellulose membranes (NFC) were used as the dielectric layer of the memory transistors (NFC), one with no additives, one with an added polymer PAE and one with added HCl. Gallium indium zinc oxide (GIZO) was used as the device’s semiconductor and gallium aluminium zinc oxide (GAZO) was used as the gate electrode. Fourier transform infrared spectroscopy (FTIR) was used to access the water content of the paper membranes before and after vacuum. It was found that the devices recovered their water too quickly for a difference to be noticeable in FTIR. The transistor’s electrical performance tests yielded a maximum ION/IOFF ratio of around 3,52x105 and a maximum subthreshold swing of 0,804 V/decade. The retention time of the dielectric charge that grants the transistor its memory capabilities was accessed by the measurement of the drain current periodically during 144 days. During this period the mean drain current did not lower, leaving the retention time of the device indeterminate. These results were compared with similar devices revealing these devices to be at the top tier of the state-of-the-art.
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Dissertação para obtenção do Grau de Doutor em Engenharia dos Materiais, especialidade Microelectrónica e Optoelectrónica, pela Universidade Nova de Lisboa, Faculdade de Ciências e Tecnologia
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Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores
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Dissertation presented to obtain a Ph.D. Degree in Chemical Physics
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Advanced Materials, Vol. 17, nº 5
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Dissertação apresentada para obtenção do Grau de Doutor em Engenharia Física - Física Aplicada pela Universidade Nova de Lisboa, Faculdade de Ciências e Tecnologia
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Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de Computadores
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Thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the subject of Electrical and Computer Engineering by the Universidade Nova de Lisboa,Faculdade de Ciências e Tecnologia
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Dissertation presented at Faculdade de Ciências e Tecnologia of Universidade Nova de Lisboa to obtain the Degree of Master in Chemical and Biochemical Engineering