Levantamento, reparação e beneficiação do simulador TERCO PST 2200 do Laboratório de Sistemas de Energia do ISEP

Este trabalho é baseado no simulador de redes PST2200 do Laboratório de Sistemas de Energia (LSE) pois está avariado com vários problemas conhecidos, designadamente: - Defeito de isolamento (disparo de diferencial), - Desregulação da velocidade da máquina primária (motor DC), - Circuito de excitação da máquina síncrona inoperacional, - Inexistência de esquemas elétricos dos circuitos do simulador, - Medidas desreguladas e com canais de medida com circuito impresso queimado. O trabalho executado foi: - O levantamento e desenho de raiz (não existe qualquer manual) dos esquemas dos 10 módulos do simulador, designadamente naqueles com avaria ou com desempenho problemático a fim de que se possa ter uma visão mais pormenorizada dos circuitos e seus problemas, por forma a intervir para os minimizar e resolver, - Foi realizado o diagnóstico de avaria do simulador e foram propostas soluções para os mesmos, - Realizaram-se as intervenções propostas e aprovadas. Nas intervenções realizadas, os princípios orientadores foram: - Aumentar a robustez do equipamento por forma a garantir a sua integridade a utilizações menos apropriados e manobras 'exóticas' próprias de alunos, que pela sua condição, estão em fase de aprendizagem, - Atualizar o equipamento, colocando-o em sintonia com o 'estado da arte', - Como fator de valorização suplementar, foi concebida e aplicada a supervisão remota do funcionamento do simulador através da rede informática. Foram detetados inúmeros erros: - Má ligação do motor de corrente continua ao variador, resultando a falta de controlo da frequência da rede do sistema, - Ligações entre painéis trocadas resultando em avarias diversas das fontes de alimentação, - Cartas eletrónicas de medidas avariadas e que além de se reparar, foram também calibradas. Devido ao mecenato da empresa Schnitt + Sohn participando monetariamente, fez-se o projeto de alteração e respetiva execução de grande parte do simulador aumentando a fiabilidade do mesmo, diminuindo assim a frequência das avarias naturais mais as que acontecem involuntariamente devido a este ser um instrumento didático. Além do trabalho elétrico, foi feito muito trabalho de chaparia para alteração de estrutura e suporte do material com diferenças de posicionamento. Neste trabalho dá-se também alguns exemplos de cálculo e simulação das redes de transporte que se pode efetuar no simulador como estudo e simulação de avarias num sistema produtivo real. Realizou-se a monitorização de dois aparelhos indicadores de parâmetros de energia (Janitza UMG96S) através duma rede com dois protocolos ethernet e profibus utilizando o plc (Omron CJ2M) como valorização do trabalho.

Controllability results for impulsive mixed type functional integro-differential evolution equations with nonlocal conditions

In this paper, we establish the controllability for a class of abstract impulsive mixed-type functional integro-differential equations with finite delay in a Banach space. Some sufficient conditions for controllability are obtained by using the Mönch fixed point theorem via measures of noncompactness and semigroup theory. Particularly, we do not assume the compactness of the evolution system. An example is given to illustrate the effectiveness of our results.

Combined mutation differential evolution to solve systems of nonlinear equations

This paper presents a differential evolution heuristic to compute a solution of a system of nonlinear equations through the global optimization of an appropriate merit function. Three different mutation strategies are combined to generate mutant points. Preliminary numerical results show the effectiveness of the presented heuristic.

Multi-μ: an Ada 95 based architecture for fault tolerance support of real-time systems

This paper presents an architecture (Multi-μ) being implemented to study and develop software based fault tolerant mechanisms for Real-Time Systems, using the Ada language (Ada 95) and Commercial Off-The-Shelf (COTS) components. Several issues regarding fault tolerance are presented and mechanisms to achieve fault tolerance by software active replication in Ada 95 are discussed. The Multi-μ architecture, based on a specifically proposed Fault Tolerance Manager (FTManager), is then described. Finally, some considerations are made about the work being done and essential future developments.

Experimenting through the web a linear variable differential transformer

Aiming for teaching/learning support in sciences and engineering areas, the Remote Experimentation concept (an E-learning subset) has grown in last years with the development of several infrastructures that enable doing practical experiments from anywhere and anytime, using a simple PC connected to the Internet. Nevertheless, given its valuable contribution to the teaching/learning process, the development of more infrastructures should continue, in order to make available more solutions able to improve courseware contents and motivate students for learning. The work presented in this paper contributes for that purpose, in the specific area of industrial automation. After a brief introduction to the Remote Experimentation concept, we describe a remote accessible lab infrastructure that enables users to conduct real experiments with an important and widely used transducer in industrial automation, named Linear Variable Differential Transformer.

A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures

On-chip debug (OCD) features are frequently available in modern microprocessors. Their contribution to shorten the time-to-market justifies the industry investment in this area, where a number of competing or complementary proposals are available or under development, e.g. NEXUS, CJTAG, IJTAG. The controllability and observability features provided by OCD infrastructures provide a valuable toolbox that can be used well beyond the debugging arena, improving the return on investment rate by diluting its cost across a wider spectrum of application areas. This paper discusses the use of OCD features for validating fault tolerant architectures, and in particular the efficiency of various fault injection methods provided by enhanced OCD infrastructures. The reference data for our comparative study was captured on a workbench comprising the 32-bit Freescale MPC-565 microprocessor, an iSYSTEM IC3000 debugger (iTracePro version) and the Winidea 2005 debugging package. All enhanced OCD infrastructures were implemented in VHDL and the results were obtained by simulation within the same fault injection environment. The focus of this paper is on the comparative analysis of the experimental results obtained for various OCD configurations and debugging scenarios.

Real time fault injection using a modified debugging infrastructure

Dependability is a critical factor in computer systems, requiring high quality validation & verification procedures in the development stage. At the same time, digital devices are getting smaller and access to their internal signals and registers is increasingly complex, requiring innovative debugging methodologies. To address this issue, most recent microprocessors include an on-chip debug (OCD) infrastructure to facilitate common debugging operations. This paper proposes an enhanced OCD infrastructure with the objective of supporting the verification of fault-tolerant mechanisms through fault injection campaigns. This upgraded on-chip debug and fault injection (OCD-FI) infrastructure provides an efficient fault injection mechanism with improved capabilities and dynamic behavior. Preliminary results show that this solution provides flexibility in terms of fault triggering and allows high speed real-time fault injection in memory elements

Real time fault injection using enhanced OCD -- a performance analysis

Fault injection is frequently used for the verification and validation of dependable systems. When targeting real time microprocessor based systems the process becomes significantly more complex. This paper proposes two complementary solutions to improve real time fault injection campaign execution, both in terms of performance and capabilities. The methodology is based on the use of the on-chip debug mechanisms present in modern electronic devices. The main objective is the injection of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented and compared in terms of performance gain and logic overhead.

Using NEXUS compliant debuggers for real time fault injection on microprocessors

As electronic devices get smaller and more complex, dependability assurance is becoming fundamental for many mission critical computer based systems. This paper presents a case study on the possibility of using the on-chip debug infrastructures present in most current microprocessors to execute real time fault injection campaigns. The proposed methodology is based on a debugger customized for fault injection and designed for maximum flexibility, and consists of injecting bit-flip type faults on memory elements without modifying or halting the target application. The debugger design is easily portable and applicable to different architectures, providing a flexible and efficient mechanism for verifying and validating fault tolerant components.

Automated design of microwave discrete tuning differential capacitance circuits in Si-integrated technologies

A genetic algorithm used to design radio-frequency binary-weighted differential switched capacitor arrays (RFDSCAs) is presented in this article. The algorithm provides a set of circuits all having the same maximum performance. This article also describes the design, implementation, and measurements results of a 0.25 lm BiCMOS 3-bit RFDSCA. The experimental results show that the circuit presents the expected performance up to 40 GHz. The similarity between the evolutionary solutions, circuit simulations, and measured results indicates that the genetic synthesis method is a very useful tool for designing optimum performance RFDSCAs.

Real-time fault injection using enhanced on-chip debug infrastructures

The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and sometimes real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on-chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off-The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concerning performance gain and silicon overhead.

Automated synthesis procedure of RF discrete tuning differential capacitance circuits

The paper presents a RFDSCA automated synthesis procedure. This algorithm determines several RFDSCA circuits from the top-level system specifications all with the same maximum performance. The genetic synthesis tool optimizes a fitness function proportional to the RFDSCA quality factor and uses the epsiv-concept and maximin sorting scheme to achieve a set of solutions well distributed along a non-dominated front. To confirm the results of the algorithm, three RFDSCAs were simulated in SpectreRF and one of them was implemented and tested. The design used a 0.25 mum BiCMOS process. All the results (synthesized, simulated and measured) are very close, which indicate that the genetic synthesis method is a very useful tool to design optimum performance RFDSCAs.

A framework for fault tolerant real time systems based on reconfigurable FPGAs

To increase the amount of logic available to the users in SRAM-based FPGAs, manufacturers are using nanometric technologies to boost logic density and reduce costs, making its use more attractive. However, these technological improvements also make FPGAs particularly vulnerable to configuration memory bit-flips caused by power fluctuations, strong electromagnetic fields and radiation. This issue is particularly sensitive because of the increasing amount of configuration memory cells needed to define their functionality. A short survey of the most recent publications is presented to support the options assumed during the definition of a framework for implementing circuits immune to bit-flips induction mechanisms in memory cells, based on a customized redundant infrastructure and on a detection-and-fix controller.

A modified debugging infrastructure to assist real time fault injection campaigns

Fault injection is frequently used for the verification and validation of the fault tolerant features of microprocessors. This paper proposes the modification of a common on-chip debugging (OCD) infrastructure to add fault injection capabilities and improve performance. The proposed solution imposes a very low logic overhead and provides a flexible and efficient mechanism for the execution of fault injection campaigns, being applicable to different target system architectures.

An automated maneuver control framework for a remotely operated vehicle

OCEANS, 2001. MTS/IEEE Conference and Exhibition (Volume:2 )