Towards network-on-chip agreement protocols

Demands for functionality enhancements, cost reductions and power savings clearly suggest the introduction of multiand many-core platforms in real-time embedded systems. However, when compared to uni-core platforms, the manycores experience additional problems, namely the lack of scalable coherence mechanisms and the necessity to perform migrations. These problems have to be addressed before such systems can be considered for integration into the realtime embedded domain. We have devised several agreement protocols which solve some of the aforementioned issues. The protocols allow the applications to plan and organise their future executions both temporally and spatially (i.e. when and where the next job will be executed). Decisions can be driven by several factors, e.g. load balancing, energy savings and thermal issues. All presented protocols are analytically described, with the particular emphasis on their respective real-time behaviours and worst-case performance. The underlying assumptions are based on the multi-kernel model and the message-passing paradigm, which constitutes the communication between the interacting instances.

A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures

On-chip debug (OCD) features are frequently available in modern microprocessors. Their contribution to shorten the time-to-market justifies the industry investment in this area, where a number of competing or complementary proposals are available or under development, e.g. NEXUS, CJTAG, IJTAG. The controllability and observability features provided by OCD infrastructures provide a valuable toolbox that can be used well beyond the debugging arena, improving the return on investment rate by diluting its cost across a wider spectrum of application areas. This paper discusses the use of OCD features for validating fault tolerant architectures, and in particular the efficiency of various fault injection methods provided by enhanced OCD infrastructures. The reference data for our comparative study was captured on a workbench comprising the 32-bit Freescale MPC-565 microprocessor, an iSYSTEM IC3000 debugger (iTracePro version) and the Winidea 2005 debugging package. All enhanced OCD infrastructures were implemented in VHDL and the results were obtained by simulation within the same fault injection environment. The focus of this paper is on the comparative analysis of the experimental results obtained for various OCD configurations and debugging scenarios.

Real-time fault injection using enhanced on-chip debug infrastructures

The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and sometimes real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on-chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off-The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concerning performance gain and silicon overhead.

Partitioning the Network-on-Chip to Enable Virtualization on Many-Core Processors

6th International Real-Time Scheduling Open Problems Seminar (RTSOPS 2015), Lund, Sweden.

Canções / Songs: Fernando Pessoa traduz António Botto

Dissertação apresentada com vista à obtenção do grau de Mestre em Tradução e Interpretação Especializada. Instituto Politécnico do Porto (Portaria nº 602/2003 de 21 Julho)

Futebol: o caminho de África até à Europa

Similarly to its past, Africa plays a similar role in the football world as it did during History, if we look at the creation of some of the most powerful empires in the world (the Portuguese, French or English, for example) – as an almost unlimited workforce ‘supplier’. Africa is still searching for its own place in the football world map. With a recent history filled with social conflicts, civil wars and racial discrimination, it was possibly in this continent that the sport was first seen as a means towards social evolution and as ‘peacemaker’. Although these problems also exist in African stadiums, supporters all over the continent go to matches to celebrate and socialize; in a reality constantly shrouded in conflicts and oppression, football is like a ‘light at the end of the tunnel’ to those who believe in a continent sustained by healthy political relations between countries, democratic values and a socially fair ‘use’ of a country’s potential – and always for the profit of its own people. But while see the attempt to use football with that objective, others see it as their ticket out of their country, to avoid getting involved in military conflicts and seek better life conditions for themselves and their families (both those who accompany them and those who remain in Africa). Others, still, try to make the most of others’ will to leave a less favourable social reality; Portugal, for its past as a colonizing country, also saw in the African players a way to develop the football phenomenon in its European territory. This article attempts to analyze the influence of Portuguese colonialism in the emigration of African players to Europe, since Portugal presents itself as one of the biggest ‘importers’ of these players.

Aplicação de dispositivos analógicos reconfiguráveis

Mestrado em Engenharia Electrotécnica e de Computadores

Nostalgia Studio. A game engine for creating collaborative multiplayer online graphic adventure games

No decorrer do projeto SELEAG foi desenvolvido um jogo de aventura gráfica educativo com o propósito de ensinar história, cultura e relações sociais aos alunos. Este jogo foi avaliado em contexto de sala de aula em diversos países, obtendo resultados positivos. No entanto, por motivos técnicos, alguns dos objetivos propostos pelo projeto não puderam ser devidamente explorados, como permitir que o jogo fosse extensível por outros educadores ou suportar a colaboração online entre os jogadores. Nomeadamente, as ferramentas utilizadas para desenvolver o jogo eram demasiado complicadas para serem utilizadas fora da equipa de desenvolvimento, o que limitou a extensibilidade do projeto, e tornou impossível que educadores sem conhecimentos de programação fossem também capazes de traduzir os seus conteúdos educativos para este formato. Além disso, apesar do jogo possuir algumas funcionalidades de colaboração online, toda a interação era efetuada externamente ao jogo, através de um fórum de mensagens, o que demonstrou ser pouco motivante para os jogadores, pois muitos deles nem se aperceberam que havia uma componente de colaboração no jogo. O objetivo desta tese incide sobre estes dois problemas, e consistiu em desenvolver um editor e motor de jogo com uma interface simples de utilizar, que não necessita de conhecimentos prévios de programação, e que permite criar jogos de aventura gráfica com uma componente de colaboração online verdadeiramente embebida na jogabilidade. A aplicação desenvolvida foi testada por um conjunto de utilizadores de diversas áreas, tendo-se obtido resultados que demonstram a acessibilidade e simplicidade da mesma, independentemente do nível de experiência prévio de programação do utilizador. A componente de colaboração online foi também muito bem recebida pelos utilizadores, os quais demonstraram bastante interesse em ver jogos de aventura gráfica com componente de colaboração online serem desenvolvidos no futuro.

Multiprocessor platform using LEON3 processor

The recent advances in embedded systems world, lead us to more complex systems with application specific blocks (IP cores), the System on Chip (SoC) devices. A good example of these complex devices can be encountered in the cell phones that can have image processing cores, communication cores, memory card cores, and others. The need of augmenting systems’ processing performance with lowest power, leads to a concept of Multiprocessor System on Chip (MSoC) in which the execution of multiple tasks can be distributed along various processors. This thesis intends to address the creation of a synthesizable multiprocessing system to be placed in a FPGA device, providing a good flexibility to tailor the system to a specific application. To deliver a multiprocessing system, will be used the synthesisable 32-bit SPARC V8 compliant, LEON3 processor.

O Dilema de clio: uma leitura paratextual do romance histórico Herculaniano

Pretende-se, neste estudo, analisar o pensamento historiográfico de Alexandre Herculano, a partir dos paratextos com que o escritor enriqueceu a sua obra de ficção. Com esta análise pretende-se mostrar como o historiador Alexandre Herculano pensava a história, como sentia as limitações impostas pelo paradigma científico que, na sua época, dominava ou pretendia dominar todas as áreas do saber, e como se viu forçado a recorrer ao romance histórico para, juntando-o à história, produzir a síntese do homem global que perseguia.

Regulation of histone H2A.Z expression is mediated by sirtuin 1 in prostate cancer

Histone variants seem to play a major role in gene expression regulation. In prostate cancer, H2A.Z and its acetylated form are implicated in oncogenes’ upregulation. SIRT1, which may act either as tumor suppressor or oncogene, reduces H2A.Z levels in cardiomyocytes, via proteasome-mediated degradation, and this mechanism might be impaired in prostate cancer cells due to sirtuin 1 downregulation. Thus, we aimed to characterize the mechanisms underlying H2A.Z and SIRT1 deregulation in prostate carcinogenesis and how they interact. We found that H2AFZ and SIRT1 were up- and downregulated, respectively, at transcript level in primary prostate cancer and high-grade prostatic intraepithelial neoplasia compared to normal prostatic tissues. Induced SIRT1 overexpression in prostate cancer cell lines resulted in almost complete absence of H2A.Z. Inhibition of mTOR had a modest effect on H2A.Z levels, but proteasome inhibition prevented the marked reduction of H2A.Z due to sirtuin 1 overexpression. Prostate cancer cells exposed to epigenetic modifying drugs trichostatin A, alone or combined with 5-aza-2’-deoxycytidine, increased H2AFZ transcript, although with a concomitant decrease in protein levels. Conversely, SIRT1 transcript and protein levels increased after exposure. ChIP revealed an increase of activation marks within the TSS region for both genes. Remarkably, inhibition of sirtuin 1 with nicotinamide, increased H2A.Z levels, whereas activation of sirtuin 1 by resveratrol led to an abrupt decrease in H2A.Z. Finally, protein-ligation assay showed that exposure to epigenetic modifying drugs fostered the interaction between sirtuin 1 and H2A.Z. We concluded that sirtuin 1 and H2A.Z deregulation in prostate cancer are reciprocally related. Epigenetic mechanisms, mostly histone post-translational modifications, are likely involved and impair sirtuin 1-mediated downregulation of H2A.Z via proteasome-mediated degradation. Epigenetic modifying drugs in conjunction with enzymatic modulators are able to restore the normal functions of sirtuin 1 and might constitute relevant tools for targeted therapy of prostate cancer patients

Application mapping in NoC-Based many-cores

Many-core platforms based on Network-on-Chip (NoC [Benini and De Micheli 2002]) present an emerging technology in the real-time embedded domain. Although the idea to group the applications previously executed on separated single-core devices, and accommodate them on an individual many-core chip offers various options for power savings, cost reductions and contributes to the overall system flexibility, its implementation is a non-trivial task. In this paper we address the issue of application mapping onto a NoCbased many-core platform when considering fundamentals and trends of current many-core operating systems, specifically, we elaborate on a limited migrative application model encompassing a message-passing paradigm as a communication primitive. As the main contribution, we formulate the problem of real-time application mapping, and propose a three-stage process to efficiently solve it. Through analysis it is assured that derived solutions guarantee the fulfilment of posed time constraints regarding worst-case communication latencies, and at the same time provide an environment to perform load balancing for e.g. thermal, energy, fault tolerance or performance reasons.We also propose several constraints regarding the topological structure of the application mapping, as well as the inter- and intra-application communication patterns, which efficiently solve the issues of pessimism and/or intractability when performing the analysis.

Preemption-light multiprocessor scheduling of sporadic tasks with high utilisation bound

Known algorithms capable of scheduling implicit-deadline sporadic tasks over identical processors at up to 100% utilisation invariably involve numerous preemptions and migrations. To the challenge of devising a scheduling scheme with as few preemptions and migrations as possible, for a given guaranteed utilisation bound, we respond with the algorithm NPS-F. It is configurable with a parameter, trading off guaranteed schedulable utilisation (up to 100%) vs preemptions. For any possible configuration, NPS-F introduces fewer preemptions than any other known algorithm matching its utilisation bound. A clustered variant of the algorithm, for systems made of multicore chips, eliminates (costly) off-chip task migrations, by dividing processors into disjoint clusters, formed by cores on the same chip (with the cluster size being a parameter). Clusters are independently scheduled (each, using non-clustered NPS-F). The utilisation bound is only moderately affected. We also formulate an important extension (applicable to both clustered and non-clustered NPS-F) which optimises the supply of processing time to executing tasks and makes it more granular. This reduces processing capacity requirements for schedulability without increasing preemptions.

Software transactional memory as a building block for parallel embedded realtime systems

The recent trends of chip architectures with higher number of heterogeneous cores, and non-uniform memory/non-coherent caches, brings renewed attention to the use of Software Transactional Memory (STM) as a fundamental building block for developing parallel applications. Nevertheless, although STM promises to ease concurrent and parallel software development, it relies on the possibility of aborting conflicting transactions to maintain data consistency, which impacts on the responsiveness and timing guarantees required by embedded real-time systems. In these systems, contention delays must be (efficiently) limited so that the response times of tasks executing transactions are upper-bounded and task sets can be feasibly scheduled. In this paper we assess the use of STM in the development of embedded real-time software, defending that the amount of contention can be reduced if read-only transactions access recent consistent data snapshots, progressing in a wait-free manner. We show how the required number of versions of a shared object can be calculated for a set of tasks. We also outline an algorithm to manage conflicts between update transactions that prevents starvation.

A parallel programming model for ada

Over the last three decades, computer architects have been able to achieve an increase in performance for single processors by, e.g., increasing clock speed, introducing cache memories and using instruction level parallelism. However, because of power consumption and heat dissipation constraints, this trend is going to cease. In recent times, hardware engineers have instead moved to new chip architectures with multiple processor cores on a single chip. With multi-core processors, applications can complete more total work than with one core alone. To take advantage of multi-core processors, parallel programming models are proposed as promising solutions for more effectively using multi-core processors. This paper discusses some of the existent models and frameworks for parallel programming, leading to outline a draft parallel programming model for Ada.