4 resultados para Nanometric CeO

em Instituto Politécnico do Porto, Portugal


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Zero-valent iron nanoparticles (nZVIs) are often used in environmental remediation. Their high surface area that is associated with their high reactivity makes them an excellent agent capable of transforming/degrading contaminants in soils and waters. Due to the recent development of green methods for the production of nZVIs, the use of this material became even more attractive. However, the knowledge of its capacity to degrade distinct types of contaminants is still scarce. The present work describes the study of the application of green nZVIs to the remediation of soils contaminated with a common anti-inflammatory drug, ibuprofen. The main objectives of this work were to produce nZVIs using extracts of grape marc, black tea and vine leaves, to verify the degradation of ibuprofen in aqueous solutions by the nZVIs, to study the remediation process of a sandy soil contaminated with ibuprofen using the nZVIs, and to compare the experiments with other common chemical oxidants. The produced nZVIs had nanometric sizes and were able to degrade ibuprofen (54 to 66% of the initial amount) in aqueous solutions. Similar remediation efficiencies were obtained in sandy soils. In this case the remediation could be enhanced (achieving degradation efficiencies above 95%) through the complementation of the process with a catalyzed nZVI Fenton-like reaction. These results indicate that this remediation technology represents a good alternative to traditional and more aggressive technologies.

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To boost logic density and reduce per unit power consumption SRAM-based FPGAs manufacturers adopted nanometric technologies. However, this technology is highly vulnerable to radiation-induced faults, which affect values stored in memory cells, and to manufacturing imperfections. Fault tolerant implementations, based on Triple Modular Redundancy (TMR) infrastructures, help to keep the correct operation of the circuit. However, TMR is not sufficient to guarantee the safe operation of a circuit. Other issues like module placement, the effects of multi- bit upsets (MBU) or fault accumulation, have also to be addressed. In case of a fault occurrence the correct operation of the affected module must be restored and/or the current state of the circuit coherently re-established. A solution that enables the autonomous restoration of the functional definition of the affected module, avoiding fault accumulation, re-establishing the correct circuit state in real-time, while keeping the normal operation of the circuit, is presented in this paper.

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To increase the amount of logic available in SRAM-based FPGAs manufacturers are using nanometric technologies to boost logic density and reduce prices. However, nanometric scales are highly vulnerable to radiation-induced faults that affect values stored in memory cells. Since the functional definition of FPGAs relies on memory cells, they become highly prone to this type of faults. Fault tolerant implementations, based on triple modular redundancy (TMR) infrastructures, help to keep the correct operation of the circuit. However, TMR is not sufficient to guarantee the safe operation of a circuit. Other issues like the effects of multi-bit upsets (MBU) or fault accumulation, have also to be addressed. Furthermore, in case of a fault occurrence the correct operation of the affected module must be restored and the current state of the circuit coherently re-established. A solution that enables the autonomous correct restoration of the functional definition of the affected module, avoiding fault accumulation, re-establishing the correct circuit state in realtime, while keeping the normal operation of the circuit, is presented in this paper.

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To increase the amount of logic available to the users in SRAM-based FPGAs, manufacturers are using nanometric technologies to boost logic density and reduce costs, making its use more attractive. However, these technological improvements also make FPGAs particularly vulnerable to configuration memory bit-flips caused by power fluctuations, strong electromagnetic fields and radiation. This issue is particularly sensitive because of the increasing amount of configuration memory cells needed to define their functionality. A short survey of the most recent publications is presented to support the options assumed during the definition of a framework for implementing circuits immune to bit-flips induction mechanisms in memory cells, based on a customized redundant infrastructure and on a detection-and-fix controller.