A New Approach to Monitoring Touristic and Cultural Routes: The Challenge of Development and Use of Indicators-Based Systems

The present paper results of an ongoing research project were it is expected to develop an information system to monitoring a cultural-touristic route. The route to monitor is the Romanesque Route of Tâmega. This Route is composed of 58 monuments located in the region of Tâmega in the North of Portugal. Due to the particular location of this region, that is between coastal zone, but not yet in the inland, it has a weak political influence, and it is reflected in the low levels of development at several levels, observed. The Romanesque Route was implemented in a part of this region in 1998, and enlarged to the all-region in 2010. In order to evaluate the socio-ecomonic impact of this route in the region a research project is being developed. The main goal of this paper is to open a discussion on the elements that must be taken into consideration to evaluate the economic and social impact of a touristic cultural route within a region and this one in particular.

Levantamento, reparação e beneficiação do simulador TERCO PST 2200 do Laboratório de Sistemas de Energia do ISEP

Este trabalho é baseado no simulador de redes PST2200 do Laboratório de Sistemas de Energia (LSE) pois está avariado com vários problemas conhecidos, designadamente: - Defeito de isolamento (disparo de diferencial), - Desregulação da velocidade da máquina primária (motor DC), - Circuito de excitação da máquina síncrona inoperacional, - Inexistência de esquemas elétricos dos circuitos do simulador, - Medidas desreguladas e com canais de medida com circuito impresso queimado. O trabalho executado foi: - O levantamento e desenho de raiz (não existe qualquer manual) dos esquemas dos 10 módulos do simulador, designadamente naqueles com avaria ou com desempenho problemático a fim de que se possa ter uma visão mais pormenorizada dos circuitos e seus problemas, por forma a intervir para os minimizar e resolver, - Foi realizado o diagnóstico de avaria do simulador e foram propostas soluções para os mesmos, - Realizaram-se as intervenções propostas e aprovadas. Nas intervenções realizadas, os princípios orientadores foram: - Aumentar a robustez do equipamento por forma a garantir a sua integridade a utilizações menos apropriados e manobras 'exóticas' próprias de alunos, que pela sua condição, estão em fase de aprendizagem, - Atualizar o equipamento, colocando-o em sintonia com o 'estado da arte', - Como fator de valorização suplementar, foi concebida e aplicada a supervisão remota do funcionamento do simulador através da rede informática. Foram detetados inúmeros erros: - Má ligação do motor de corrente continua ao variador, resultando a falta de controlo da frequência da rede do sistema, - Ligações entre painéis trocadas resultando em avarias diversas das fontes de alimentação, - Cartas eletrónicas de medidas avariadas e que além de se reparar, foram também calibradas. Devido ao mecenato da empresa Schnitt + Sohn participando monetariamente, fez-se o projeto de alteração e respetiva execução de grande parte do simulador aumentando a fiabilidade do mesmo, diminuindo assim a frequência das avarias naturais mais as que acontecem involuntariamente devido a este ser um instrumento didático. Além do trabalho elétrico, foi feito muito trabalho de chaparia para alteração de estrutura e suporte do material com diferenças de posicionamento. Neste trabalho dá-se também alguns exemplos de cálculo e simulação das redes de transporte que se pode efetuar no simulador como estudo e simulação de avarias num sistema produtivo real. Realizou-se a monitorização de dois aparelhos indicadores de parâmetros de energia (Janitza UMG96S) através duma rede com dois protocolos ethernet e profibus utilizando o plc (Omron CJ2M) como valorização do trabalho.

Multi-μ: an Ada 95 based architecture for fault tolerance support of real-time systems

This paper presents an architecture (Multi-μ) being implemented to study and develop software based fault tolerant mechanisms for Real-Time Systems, using the Ada language (Ada 95) and Commercial Off-The-Shelf (COTS) components. Several issues regarding fault tolerance are presented and mechanisms to achieve fault tolerance by software active replication in Ada 95 are discussed. The Multi-μ architecture, based on a specifically proposed Fault Tolerance Manager (FTManager), is then described. Finally, some considerations are made about the work being done and essential future developments.

A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures

On-chip debug (OCD) features are frequently available in modern microprocessors. Their contribution to shorten the time-to-market justifies the industry investment in this area, where a number of competing or complementary proposals are available or under development, e.g. NEXUS, CJTAG, IJTAG. The controllability and observability features provided by OCD infrastructures provide a valuable toolbox that can be used well beyond the debugging arena, improving the return on investment rate by diluting its cost across a wider spectrum of application areas. This paper discusses the use of OCD features for validating fault tolerant architectures, and in particular the efficiency of various fault injection methods provided by enhanced OCD infrastructures. The reference data for our comparative study was captured on a workbench comprising the 32-bit Freescale MPC-565 microprocessor, an iSYSTEM IC3000 debugger (iTracePro version) and the Winidea 2005 debugging package. All enhanced OCD infrastructures were implemented in VHDL and the results were obtained by simulation within the same fault injection environment. The focus of this paper is on the comparative analysis of the experimental results obtained for various OCD configurations and debugging scenarios.

Real time fault injection using a modified debugging infrastructure

Dependability is a critical factor in computer systems, requiring high quality validation & verification procedures in the development stage. At the same time, digital devices are getting smaller and access to their internal signals and registers is increasingly complex, requiring innovative debugging methodologies. To address this issue, most recent microprocessors include an on-chip debug (OCD) infrastructure to facilitate common debugging operations. This paper proposes an enhanced OCD infrastructure with the objective of supporting the verification of fault-tolerant mechanisms through fault injection campaigns. This upgraded on-chip debug and fault injection (OCD-FI) infrastructure provides an efficient fault injection mechanism with improved capabilities and dynamic behavior. Preliminary results show that this solution provides flexibility in terms of fault triggering and allows high speed real-time fault injection in memory elements

Real time fault injection using enhanced OCD -- a performance analysis

Fault injection is frequently used for the verification and validation of dependable systems. When targeting real time microprocessor based systems the process becomes significantly more complex. This paper proposes two complementary solutions to improve real time fault injection campaign execution, both in terms of performance and capabilities. The methodology is based on the use of the on-chip debug mechanisms present in modern electronic devices. The main objective is the injection of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented and compared in terms of performance gain and logic overhead.

Using NEXUS compliant debuggers for real time fault injection on microprocessors

As electronic devices get smaller and more complex, dependability assurance is becoming fundamental for many mission critical computer based systems. This paper presents a case study on the possibility of using the on-chip debug infrastructures present in most current microprocessors to execute real time fault injection campaigns. The proposed methodology is based on a debugger customized for fault injection and designed for maximum flexibility, and consists of injecting bit-flip type faults on memory elements without modifying or halting the target application. The debugger design is easily portable and applicable to different architectures, providing a flexible and efficient mechanism for verifying and validating fault tolerant components.

Real-time fault injection using enhanced on-chip debug infrastructures

The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and sometimes real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on-chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off-The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concerning performance gain and silicon overhead.

A framework for fault tolerant real time systems based on reconfigurable FPGAs

To increase the amount of logic available to the users in SRAM-based FPGAs, manufacturers are using nanometric technologies to boost logic density and reduce costs, making its use more attractive. However, these technological improvements also make FPGAs particularly vulnerable to configuration memory bit-flips caused by power fluctuations, strong electromagnetic fields and radiation. This issue is particularly sensitive because of the increasing amount of configuration memory cells needed to define their functionality. A short survey of the most recent publications is presented to support the options assumed during the definition of a framework for implementing circuits immune to bit-flips induction mechanisms in memory cells, based on a customized redundant infrastructure and on a detection-and-fix controller.

A modified debugging infrastructure to assist real time fault injection campaigns

Fault injection is frequently used for the verification and validation of the fault tolerant features of microprocessors. This paper proposes the modification of a common on-chip debugging (OCD) infrastructure to add fault injection capabilities and improve performance. The proposed solution imposes a very low logic overhead and provides a flexible and efficient mechanism for the execution of fault injection campaigns, being applicable to different target system architectures.

Business micro-location: factors, preferences and indicators to assess the influence factors

The paper presents a study on business micro-location behaviour as well as corresponding factors of influence, conducted in two metropolitan areas, Bucharest-Ilfov (Romania) and Greater Porto (Portugal). By business micro-location we refer to a specific site such as a building or facility, accommodating a business within a small, compact geographical area (e.g. metropolitan area). At this geographical scale, the macroeconomic layer factors were excluded, applicable when discern between regions or countries. The factors derived from location theory and previous empirical studies were surveyed, completing a cross-sectional analysis in order to find out the specific weights of the location factors and preferences, by region and by industry. Based on already established firms’ feedback on location, the specific weights were granted by each industry to the main location factors, types of areas, and types of accommodation facilities. The authors also suggested a model to integrate these results into a Geographical Information System (GIS).

Acqusition and data analysis of the eco-efficiency for the establishment of indicators parameters for industrial environmental sustainability

The industrial activity is inevitably associated with a certain degradation of the environmental quality, because is not possible to guarantee that a manufacturing process can be totally innocuous. The eco-efficiency concept is globally accepted as a philosophy of entreprise management, that encourages the companies to become more competitive, innovative and environmentally responsible by promoting the link between its companies objectives for excellence and its objectives of environmental excellence issues. This link imposes the creation of an organizational methodology where the performance of the company is concordant with the sustainable development. The main propose of this project is to apply the concept of eco-efficiency to the particular case of the metallurgical and metal workshop industries through the development of the particular indicators needed and to produce a manual of procedures for implementation of the accurate solution.

Deteção e identificação de anomalias em redes de distribuição de energia elétrica

Na ocorrência de anomalias nas redes de distribuição de energia elétrica, muitas vezes devido ao reduzido número de informação disponível, a determinação da localização dos defeitos é uma tarefa árdua e morosa. Consequentemente, impõe-se o recurso por parte das companhias elétricas a sistemas que, contribuindo para a diminuição do tempo despendido na localização dos defeitos, assegurem a redução da duração e frequência das falhas de alimentação. Esta dissertação pretende estudar os diversos sistemas de deteção de defeitos existentes, com destaque para a utilização de Indicadores de Passagem de Defeito e analisar o contributo destes sistemas para a melhoria dos Índices de Qualidade de Serviço. Abordar as dificuldades que se colocam à implementação destes sistemas, nomeadamente, pelas características específicas das redes de distribuição. Pretende, ainda, desenvolver uma metodologia e a respetiva ferramenta, que permita a deteção de defeitos baseada na utilização de Indicadores de Passagem de Defeito comunicantes, numa saída da rede de distribuição de média tensão pertencente à EDP. Analisar técnica e economicamente os benefícios a obter com a implementação da metodologia desenvolvida. Esta dissertação pretende, não só atingir os objetivos acima referidos, mas também, através deles, elaborar uma ferramenta útil para as Companhias Elétricas, no sentido de adotarem sistemas de deteção de defeitos e com fim principal de uma possível redução dos tempos de indisponibilidade de alimentação, intimamente associados à persecução de melhores índices de Qualidade de Serviço por parte das mesmas.

Deteção e previsão de falhas em equipamentos de produção industrial

As empresas nacionais deparam-se com a necessidade de responder ao mercado com uma grande variedade de produtos, pequenas séries e prazos de entrega reduzidos. A competitividade das empresas num mercado global depende assim da sua eficiência, da sua flexibilidade, da qualidade dos seus produtos e de custos reduzidos. Para se atingirem estes objetivos é necessário desenvolverem-se estratégias e planos de ação que envolvem os equipamentos produtivos, incluindo: a criação de novos equipamentos complexos e mais fiáveis, alteração dos equipamentos existentes modernizando-os de forma a responderem às necessidades atuais e a aumentar a sua disponibilidade e produtividade; e implementação de políticas de manutenção mais assertiva e focada no objetivo de “zero avarias”, como é o caso da manutenção preditiva. Neste contexto, o objetivo principal deste trabalho consiste na previsão do instante temporal ótimo da manutenção de um equipamento industrial – um refinador da fábrica de Mangualde da empresa Sonae Industria, que se encontra em funcionamento contínuo 24 horas por dia, 365 dias por ano. Para o efeito são utilizadas medidas de sensores que monitorizam continuamente o estado do refinador. A principal operação de manutenção deste equipamento é a substituição de dois discos metálicos do seu principal componente – o desfibrador. Consequentemente, o sensor do refinador analisado com maior detalhe é o sensor que mede a distância entre os dois discos do desfibrador. Os modelos ARIMA consistem numa abordagem estatística avançada para previsão de séries temporais. Baseados na descrição da autocorrelação dos dados, estes modelos descrevem uma série temporal como função dos seus valores passados. Neste trabalho, a metodologia ARIMA é utilizada para determinar um modelo que efetua uma previsão dos valores futuros do sensor que mede a distância entre os dois discos do desfibrador, determinando-se assim o momento ótimo da sua substituição e evitando paragens forçadas de produção por ocorrência de uma falha por desgaste dos discos. Os resultados obtidos neste trabalho constituem uma contribuição científica importante para a área da manutenção preditiva e deteção de falhas em equipamentos industriais.

Passive Fault-Tolerance Management in Component-based Embedded Systems

It is imperative to accept that failures can and will occur, even in meticulously designed distributed systems, and design proper measures to counter those failures. Passive replication minimises resource consumption by only activating redundant replicas in case of failures, as typically providing and applying state updates is less resource demanding than requesting execution. However, most existing solutions for passive fault tolerance are usually designed and configured at design time, explicitly and statically identifying the most critical components and their number of replicas, lacking the needed flexibility to handle the runtime dynamics of distributed component-based embedded systems. This paper proposes a cost-effective adaptive fault tolerance solution with a significant lower overhead compared to a strict active redundancy-based approach, achieving a high error coverage with the minimum amount of redundancy. The activation of passive replicas is coordinated through a feedback-based coordination model that reduces the complexity of the needed interactions among components until a new collective global service solution is determined, improving the overall maintainability and robustness of the system.