Real-time fault injection using enhanced on-chip debug infrastructures

The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and sometimes real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on-chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off-The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concerning performance gain and silicon overhead.

O sistema de controlo interno numa empresa do sector hoteleiro: estudo de caso: âmbito da área de vendas

Trabalho de Projecto apresentado ao Instituto de Contabilidade e Administração do Porto para a obtenção do grau de Mestre em Auditoria, sob a orientação da Doutora Alcina Augusta de Sena Portugal Dias. “Esta versão contém as críticas e sugestões dos elementos do júri”

Heading east this time: critical readings on gender in southeast Asia

This essay intends to discuss some critical readings of fictional and theoretical texts on gender condition in Southeast Asian countries. Nowadays, many texts about women in Southeast Asia apply concepts of power in unusual areas. Traditional forms of gender hegemony have been replaced by other powerful, if somewhat more covert, forms. We will discuss some universal values concerning conventional female roles as well as the strategies used to recognize women in political fields traditionally characterized by male dominance. Female empowerment will mean different things at different times in history, as a result of culture, local geography and individual circumstances. Empowerment needs to be perceived as an individual attitude, but it also has to be facilitated at the macrolevel by society and the State. Gender is very much at the heart of all these dynamics, strongly related to specificities of historical, cultural, ethnic and class situatedness, requiring an interdisciplinary transnational approach.

A relação entre a acreditação/certificação da qualidade e o controlo interno nas organizações: estudo de caso em 30 unidades hospitalares públicas portuguesas

Dissertação de Mestrado apresentado ao Instituto de Contabilidade e Administração do Porto para a obtenção do grau de Mestre em Auditoria, sob orientação de: Doutora Alcina Dias e coorientação de: Doutora Ana Paula Lopes

Parallel Software framework for time-critical many-core systems

The recent technological advancements and market trends are causing an interesting phenomenon towards the convergence of High-Performance Computing (HPC) and Embedded Computing (EC) domains. On one side, new kinds of HPC applications are being required by markets needing huge amounts of information to be processed within a bounded amount of time. On the other side, EC systems are increasingly concerned with providing higher performance in real-time, challenging the performance capabilities of current architectures. The advent of next-generation many-core embedded platforms has the chance of intercepting this converging need for predictable high-performance, allowing HPC and EC applications to be executed on efficient and powerful heterogeneous architectures integrating general-purpose processors with many-core computing fabrics. To this end, it is of paramount importance to develop new techniques for exploiting the massively parallel computation capabilities of such platforms in a predictable way. P-SOCRATES will tackle this important challenge by merging leading research groups from the HPC and EC communities. The time-criticality and parallelisation challenges common to both areas will be addressed by proposing an integrated framework for executing workload-intensive applications with real-time requirements on top of next-generation commercial-off-the-shelf (COTS) platforms based on many-core accelerated architectures. The project will investigate new HPC techniques that fulfil real-time requirements. The main sources of indeterminism will be identified, proposing efficient mapping and scheduling algorithms, along with the associated timing and schedulability analysis, to guarantee the real-time and performance requirements of the applications.