eTourism – Mobile Data Interface (Sistema de Apoio On-Line ao Turista em Dispositivos Móveis com Adaptação de Tours Personalizados)

O intuito principal desta Tese é criar um interface de Dados entre uma fonte de informação e fornecimento de Rotas para turistas e disponibilizar essa informação através de um sistema móvel interactivo de navegação e visualização desses mesmos dados. O formato tecnológico será portátil e orientado à mobilidade (PDA) e deverá ser prático, intuitivo e multi-facetado, permitindo boa usabilidade a públicos de várias faixas etárias. Haverá uma componente de IA (Inteligência Artificial), que irá usar a informação fornecida para tomar decisões ponderadas tendo em conta uma diversidade de aspectos. O Sistema a desenvolver deverá ser, assim, capaz de lidar com imponderáveis (alterações de rota, gestão de horários, cancelamento de pontos de visita, novos pontos de visita) e, finalmente, deverá ajudar o turista a gerir o seu tempo entre Pontos de Interesse (POI – Points os Interest). Deverá também permitir seguir ou não um dado percurso pré-definido, havendo possibilidade de cenários de exploração de POIs, sugeridos a partir de sugestões in loco, similares a Locais incluídos no trajecto, que se enquadravam no perfil dos Utilizadores. O âmbito geográfico de teste deste projecto será a zona ribeirinha do porto, por ser um ex-líbris da cidade e, simultaneamente, uma zona com muitos desafios ao nível geográfico (com a inclinação) e ao nível do grande número de Eventos e Locais a visitar.

Sistema de expedição automática em SAP: implementação logística na Gopaca

Este documento apresenta o desenvolvimento de um sistema que visa relacionar e interligar as tecnologias móveis, automação industrial e SAP às necessidades da Gopaca, uma empresa de produção de derivados de cartão. A empresa Gopaca demonstrou interesse e necessidade em melhorar os seus processos internos de maneira a aumentar produtividade, diminuir desperdícios e implementar uma filosofia de Lean Manufacturing. Para que isso fosse possível foram implementados novos processos em SAP de modo a automatizar todo o processo pré-produtivo, pós produtivo e expedicional, bem como implementado um sistema de Warehouse Management inovador a nível mundial no que a empresas de produção de cartão diz respeito. Sendo expectável que após a conclusão do projecto os resultados fossem inegáveis em termos de aplicação da metodologia Lean Manufacturing. Foram efectuadas melhorias na forma como a entrada de mercadoria e produção é feita em SAP, passando de completamente manual para completamente automática, até à forma como a expedição será feita, apenas necessitando de um operador com uma pistola de leitura de códigos de barra para despoletar o processo completo até ao momento de impressão da guia de transporte. Todo este processo é inovador no que diz respeito à sua implementação em SAP com o foco no desejo do cliente, não existindo ainda, nenhum produto (modulo SAP) no mercado que permita a execução automática dos processos indicados. Todos os processos se tornaram simples e intuitivos e na maior parte dos casos sem qualquer necessidade de interacção com o utilizador, reduzindo o tempo anteriormente despendido nesta operações, podendo este ser aplicado nas áreas onde é realmente necessário.

Modelação do transporte e dispersão de um marcador corado no Rio Febros

O rio Febros é um pequeno curso de água, situado no concelho de Vila Nova de Gaia, com cerca de 15 km de extensão, cuja bacia hidrográfica ocupa uma área de aproximadamente 35,4 km2. Nasce em Seixezelo e desagua na margem esquerda do Rio Douro no Cais do Esteiro, em Avintes. Em Maio de 2008, um acidente de viação teve como consequência o derrame de cerca de quatro toneladas de ácido clorídrico que rapidamente convergiu às águas do rio. Apenas um dia depois, o pH desceu para três e muitos foram os peixes que morreram. A solução adoptada para evitar o desaire foi introduzir milhares de litros de água de modo a diluir o ácido presente, ao longo de todo o curso de água. Tal facto não evitou a destruição de parte de um ecossistema, que ainda nos dias de hoje se encontra em recuperação. De forma a avaliar-se o impacto destas possíveis perturbações sejam estas de origem antropogénica ou natural é necessário possuir conhecimentos dos processos químicos tais como a advecção, a mistura devida à dispersão e a transferência de massa ar/água. Estes processos irão determinar o movimento e destino das substâncias que poderão ser descarregadas no rio. Para tal, recorrer-se-á ao estudo hidrogeométrico do curso de água assim como ao estudo do comportamento de um marcador, simulando uma possível descarga. A rodamina WT será o marcador a ser utilizado devido à panóplia de características ambientalmente favoráveis. Os estudos de campo com este corante, realizados em sequência de descarga previamente estudada, fornecem uma das melhores fontes de informação para verificação e validação de modelos hidráulicos utilizados em estudos de qualidade de águas e protecção ambiental. Escolheram-se dois pontos de descarga no Febros, um em Casal Drijo e outro no Parque Biológico de Gaia, possuindo cada um deles, a jusante, duas estações de monitorização. Pelo modelo ADE os valores obtidos para o coeficiente de dispersão longitudinal para as estações Pontão d’ Alheira, Pinheiral, Menesas e Giestas foram, respectivamente, 0,3622; 0,5468; 1,6832 e 1,7504 m2/s. Para a mesma sequência de estações, os valores da velocidade de escoamento obtidos neste trabalho experimental foram de 0,0633; 0,0684; 0,1548 e 0,1645 m/s. Quanto ao modelo TS, os valores obtidos para o coeficiente de dispersão longitudinal para as estações Pontão d’ Alheira, Pinheiral, Menesas e Giestas foram, respectivamente, 0,2339; 0,1618; 0,5057e 1,1320 m2/s. Para a mesma sequência de estações, os valores da velocidade de escoamento obtidos neste trabalho experimental foram de 0,0652; 0,0775; 0,1891 e 0,1676 m/s. Os resultados foram ajustados por um método directo, o método dos momentos, e por dois métodos indirectos, os modelos ADE e TS. O melhor ajuste corresponde ao modelo TS onde os valores do coeficiente de dispersão longitudinal e da velocidade de escoamento são aqueles que melhor se aproximam da realidade. Quanto ao método dos momentos, o valor estimado para a velocidade é de 0,162 m/s e para o coeficiente de dispersão longitudinal de 9,769 m2/s. Não obstante, a compreensão da hidrodinâmica do rio e das suas características, bem como a adequação de modelos matemáticos no tratamento de resultados formam uma estratégia de protecção ambiental inerente a futuros impactos que possam suceder.

A distributed system for learning programming on-line

Several Web-based on-line judges or on-line programming trainers have been developed in order to allow students to train their programming skills. However, their pedagogical functionalities in the learning of programming have not been clearly defined. EduJudge is a project which aims to integrate the “UVA On-line Judge”, an existing on-line programming trainer with an important number of problems and users, into an effective educational environment consisting of the e-learning platform Moodle and the competitive learning tool QUESTOURnament. The result is the EduJudge system which allows teachers to apply different pedagogical approaches using a proven e-learning platform, makes problems easy to search through an effective search engine, and provides an automated evaluation of the solutions submitted to these problems. The final objective is to provide new learning strategies to motivate students and present programming as an easy and attractive challenge. EduJudge has been tried and tested in three algorithms and programming courses in three different Engineering degrees. The students’ motivation and satisfaction levels were analysed alongside the effects of the EduJudge system on students’ academic outcomes. Results indicate that both students and teachers found that among other multiple benefits the EduJudge system facilitates the learning process. Furthermore, the experi- ment also showed an improvement in students’ academic outcomes. It must be noted that the students’ level of satisfaction did not depend on their computer skills or their gender.

Characterizing the timing behaviour of power-line communication by means of simulation

Although power-line communication (PLC) is not a new technology, its use to support communication with timing requirements is still the focus of ongoing research. Recently, a new infrastructure was presented, intended for communication using power lines from a central location to geographically dispersed nodes using inexpensive devices. This new infrastructure uses a two-level hierarchical power-line system, together with an IP-based network. Within this infrastructure, in order to provide end-toend communication through the two levels of the powerline system, it is necessary to fully understand the behaviour of the underlying network layers. The masterslave behaviour of the PLC MAC, together with the inherent dynamic topology of power-line networks are important issues that must be fully characterised. Therefore, in this paper we present a simulation model which is being used to study and characterise the behaviour of power-line communication.

A power line communication stack for metering, SCADA and large-scale domotic applications

This paper describes the communication stack of the REMPLI system: a structure using power-lines and IPbased networks for communication, for data acquisition and control of energy distribution and consumption. It is furthermore prepared to use alternative communication media like GSM or analog modem connections. The REMPLI system provides communication service for existing applications, namely automated meter reading, energy billing and domotic applications. The communication stack, consisting of physical, network, transport, and application layer is described as well as the communication services provided by the system. We show how the peculiarities of the power-line communication influence the design of the communication stack, by introducing requirements to efficiently use the limited bandwidth, optimize traffic and implement fair use of the communication medium for the extensive communication partners.

On the development of a test-bed application for the ART-WiSe architecture

The ART-WiSe (Architecture for Real-Time communications in Wireless Sensor Networks) framework aims at the design of new communication architectures and mechanisms for time-sensitive Wireless Sensor Networks (WSNs). We adopted a two-tiered architecture where an overlay Wireless Local Area Network (Tier 2) serves as a backbone for a WSN (Tier 1), relying on existing standard communication protocols and commercial-off-the-shell (COTS) technologies – IEEE 802.15.4/ZigBee for Tier 1 and IEEE 802.11 for Tier 2. In this line, a test-bed application is being developed for assessing, validating and demonstrating the ART-WiSe architecture. A pursuit-evasion application was chosen since it fulfils a number of requirements, namely it is feasible and appealing and imposes some stress to the architecture in terms of timeliness. To develop the testbed based on the previously referred technologies, an implementation of the IEEE 8021.5.4/ZigBee protocols is being carried out, since there is no open source available to the community. This paper highlights some relevant aspects of the ART-WiSe architecture, provides some intuition on the protocol stack implementation and presents a general view over the envisaged test-bed application.

Energy and delay trade-off of the GTS allocation mechanism in IEEE 802.15.4 for wireless sensor networks

The IEEE 802.15.4 protocol proposes a flexible communication solution for Low-Rate Wireless Personal Area Networks (LR-WPAN) including wireless sensor networks (WSNs). It presents the advantage to fit different requirements of potential applications by adequately setting its parameters. When in beaconenabled mode, the protocol can provide timeliness guarantees by using its Guaranteed Time Slot (GTS) mechanism. However, power-efficiency and timeliness guarantees are often two antagonistic requirements in wireless sensor networks. The purpose of this paper is to analyze and propose a methodology for setting the relevant parameters of IEEE 802.15.4-compliant WSNs that takes into account a proper trade-off between power-efficiency and delay bound guarantees. First, we propose two accurate models of service curves for a GTS allocation as a function of the IEEE 802.15.4 parameters, using Network Calculus formalism. We then evaluate the delay bound guaranteed by a GTS allocation and express it as a function of the duty cycle. Based on the relation between the delay requirement and the duty cycle, we propose a power-efficient superframe selection method that simultaneously reduces power consumption and enables meeting the delay requirements of real-time flows allocating GTSs. The results of this work may pave the way for a powerefficient management of the GTS mechanism in an IEEE 802.15.4 cluster.

Scheduling a cutting and treatment stainless steel sheet line with self-management capabilities

With advancement in computer science and information technology, computing systems are becoming increasingly more complex with an increasing number of heterogeneous components. They are thus becoming more difficult to monitor, manage, and maintain. This process has been well known as labor intensive and error prone. In addition, traditional approaches for system management are difficult to keep up with the rapidly changing environments. There is a need for automatic and efficient approaches to monitor and manage complex computing systems. In this paper, we propose an innovative framework for scheduling system management by combining Autonomic Computing (AC) paradigm, Multi-Agent Systems (MAS) and Nature Inspired Optimization Techniques (NIT). Additionally, we consider the resolution of realistic problems. The scheduling of a Cutting and Treatment Stainless Steel Sheet Line will be evaluated. Results show that proposed approach has advantages when compared with other scheduling systems

Real time fault injection using a modified debugging infrastructure

Dependability is a critical factor in computer systems, requiring high quality validation & verification procedures in the development stage. At the same time, digital devices are getting smaller and access to their internal signals and registers is increasingly complex, requiring innovative debugging methodologies. To address this issue, most recent microprocessors include an on-chip debug (OCD) infrastructure to facilitate common debugging operations. This paper proposes an enhanced OCD infrastructure with the objective of supporting the verification of fault-tolerant mechanisms through fault injection campaigns. This upgraded on-chip debug and fault injection (OCD-FI) infrastructure provides an efficient fault injection mechanism with improved capabilities and dynamic behavior. Preliminary results show that this solution provides flexibility in terms of fault triggering and allows high speed real-time fault injection in memory elements

A system verification strategy based on the BST infrastructure

A good verification strategy should bring near the simulation and real functioning environments. In this paper we describe a system-level co-verification strategy that uses a common flow for functional simulation, timing simulation and functional debug. This last step requires using a BST infrastructure, now widely available on commercial devices, specially on FPGAs with medium/large pin-counts.

Real-time fault injection using enhanced on-chip debug infrastructures

The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and sometimes real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on-chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off-The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concerning performance gain and silicon overhead.

On-line self-healing of circuits implemented on reconfigurable FPGAs

To boost logic density and reduce per unit power consumption SRAM-based FPGAs manufacturers adopted nanometric technologies. However, this technology is highly vulnerable to radiation-induced faults, which affect values stored in memory cells, and to manufacturing imperfections. Fault tolerant implementations, based on Triple Modular Redundancy (TMR) infrastructures, help to keep the correct operation of the circuit. However, TMR is not sufficient to guarantee the safe operation of a circuit. Other issues like module placement, the effects of multi- bit upsets (MBU) or fault accumulation, have also to be addressed. In case of a fault occurrence the correct operation of the affected module must be restored and/or the current state of the circuit coherently re-established. A solution that enables the autonomous restoration of the functional definition of the affected module, avoiding fault accumulation, re-establishing the correct circuit state in real-time, while keeping the normal operation of the circuit, is presented in this paper.

On-line defragmentation for run-time partially reconfigurable FPGAs

Dynamically reconfigurable systems have benefited from a new class of FPGAs recently introduced into the market, which allow partial and dynamic reconfiguration at run-time, enabling multiple independent functions from different applications to share the same device, swapping resources as needed. When the sequence of tasks to be performed is not predictable, resource allocation decisions have to be made on-line, fragmenting the FPGA logic space. A rearrangement may be necessary to get enough contiguous space to efficiently implement incoming functions, to avoid spreading their components and, as a result, degrading their performance. This paper presents a novel active replication mechanism for configurable logic blocks (CLBs), able to implement on-line rearrangements, defragmenting the available FPGA resources without disturbing those functions that are currently running.

A comunicação on-line das ONGs e a angariação de fundos

Dissertação de Mestrado apresentado ao Instituto de Contabilidade e Administração do Porto para a obtenção do grau de Mestre em Marketing Digital, sob orientação da Mestre Inês Veiga Pereira “Esta versão contém as críticas e sugestões dos elementos do júri”