Intermodulation in active reconfigurable antennas

Due to the application of active components into antennas these became a source of distortion on wireless communication systems. In this paper we explore the nonlinear effects occurring in a frequency reconfigurable antenna operating with a PIN Diode. We describe the measurement setup used to check the antenna intermodulation products and the measured compression and third order intermodulation limitations of a frequency reconfigurable antenna, operating at the UMTS and WLAN frequencies.

Compact, frequency reconfigurable, printed monopole antenna

This paper proposes a possible implementation of a compact printed monopole antenna, useful to operate in UMTS and WLAN bands. In order to accomplish that, a miniaturization technique based on the application of chip inductors is used in conjunction with frequency reconfiguration capability. The chip inductors change the impedance response of the monopole, allowing to reduce the resonant frequency. In order to be able to operate the antenna in these two different frequencies, an antenna reconfiguration technique based on PIN diodes is applied. This procedure allows the change of the active form of the antenna leading to a shift in the resonant frequency. The prototype measurements show good agreement with the simulation results.

Reconfigurable antenna for mobile terminal

Trabalho Final de Mestrado para obtenção do grau de Mestrado em Engenharia Electrónica e Telecomunicações

Sparse matrix multiplication on a reconfigurable many-core architecture

Sparse matrix-vector multiplication (SMVM) is a fundamental operation in many scientific and engineering applications. In many cases sparse matrices have thousands of rows and columns where most of the entries are zero, while non-zero data is spread over the matrix. This sparsity of data locality reduces the effectiveness of data cache in general-purpose processors quite reducing their performance efficiency when compared to what is achieved with dense matrix multiplication. In this paper, we propose a parallel processing solution for SMVM in a many-core architecture. The architecture is tested with known benchmarks using a ZYNQ-7020 FPGA. The architecture is scalable in the number of core elements and limited only by the available memory bandwidth. It achieves performance efficiencies up to almost 70% and better performances than previous FPGA designs.