A Design methodology for integrated inductor-based DC-DC converters

A design methodology for monolithic integration of inductor based DC-DC converters is proposed in this paper. A power loss model of the power stage, including the drive circuits, is defined in order to optimize efficiency. Based on this model and taking as reference a 0.35 mu m CMOS process, a buck converter was designed and fabricated. For a given set of operating conditions the defined power loss model allows to optimize the design parameters for the power stage, including the gate-driver tapering factor and the width of the power MOSFETs. Experimental results obtained from a buck converter at 100 MHz switching frequency are presented to validate the proposed methodology.

Design of improved rail-to-rail low-distortion and low-stress switches in advanced CMOS technologies

This paper describes the efficient design of an improved and dedicated switched-capacitor (SC) circuit capable of linearizing CMOS switches to allow SC circuits to reach low distortion levels. The described circuit (SC linearization control circuit, SLC) has the advantage over conventional clock-bootstrapping circuits of exhibiting low-stress, since large gate voltages are avoided. This paper presents exhaustive corner simulation results of a SC sample-and-hold (S/H) circuit which employs the proposed and optimized circuits, together with the experimental evaluation of a complete 10-bit ADC utilizing the referred S/H circuit. These results show that the SLC circuits can reduce distortion and increase dynamic linearity above 12 bits for wide input signal bandwidths.

MDAI: Model based Design in Automobile Industry

It is proposed a new approach based on a methodology, assisted by a tool, to create new products in the automobile industry based on previous defined processes and experiences inspired on a set of best practices or principles: it is based on high-level models or specifications; it is component-based architecture centric; it is based on generative programming techniques. This approach follows in essence the MDA (Model Driven Architecture) philosophy with some specific characteristics. We propose a repository that keeps related information, such as models, applications, design information, generated artifacts and even information concerning the development process itself (e.g., generation steps, tests and integration milestones). Generically, this methodology receives the users' requirements to a new product (e.g., functional, non-functional, product specification) as its main inputs and produces a set of artifacts (e.g., design parts, process validation output) as its main output, that will be integrated in the engineer design tool (e.g. CAD system) facilitating the work.

A 5GHz/1.8V CMOS Active Balun Integrated with LNA

The development of high performance monolithic RF front-ends requires innovative RF circuit design to make the best of a good technology. A fully differential approach is usually preferred, due to its well-known properties. Although the differential approach must be preserved inside the chip, there are cases where the input signal is single-ended such as RF image filters and IF filters in a RF receiver. In these situations, a stage able to convert single-ended into differential signals (balun) is needed. The most cited topology, which is capable of providing high gain, consists on a differential stage with one of the two inputs grounded. Unfortunately, this solution has some drawbacks when implemented monolithically. This work presents the design and simulated results of an innovative high-performance monolithic single to differential converter, which overcomes the limitations of the circuits.The integration of the monolithic active balun circuit with an LNA on a 0.18μm CMOS process is also reported. The circuits presented here are aimed at 802.11a. Section 2 describes the balun circuit and section 3 presents its performance when it is connected to a conventional single-ended LNA. Section 4 shows the simulated performance results focused at phase/amplitude balance and noise figure. Finally, the last section draws conclusions and future work.

Direct Color Sensor, Optical Amplifier and Demux Device Integrated on a Single Monolithic SiC Photodetector

A pi'n/pin a-SiC:H voltage and optical bias controlled device is presented and its behavior as image and color sensor, optical amplifier and demux device is discussed. The design and the light source properties are correlated with the sensor output characteristics. Different readout techniques are used. When a low power monochromatic scanner readout the generated carriers the transducer recognizes a color pattern projected on it acting as a direct color and image sensor. Scan speeds up to 10(4) lines per second are achieved without degradation in the resolution. If the photocurrent generated by different monochromatic pulsed channels is readout directly, the information is demultiplexed. Results show that it is possible to decode the information from three simultaneous color channels without bit errors at bit rates per channel higher than 4000 bps. Finally, when triggered by light of appropriated wavelength, it can amplify or suppress the generated photocurrent working as an optical amplifier (C) 2009 Published by Elsevier Ltd.

Integrated didactics: an example of a curriculum model enhancing knowledge crossing

In this paper, we introduce an innovative course in the Portuguese Context, the Master's Course in “Integrated Didactics in Mother Tongue, Maths, Natural and Social Sciences”, taking place at the Lisbon School of Education and discussing in particular the results of the evaluation made by the students who attended the Curricular Unit - Integrated Didactics (CU-ID). This course was designed for in-service teachers of the first six years of schooling and intends to improve connections between different curriculum areas. In this paper, we start to present a few general ideas about curriculum development; to discuss the concept of integration; to present the principles and objectives of the course created as well as its structure; to describe the methodology used in the evaluation process of the above mentioned CU-ID. The results allow us to state that the students recognized, as positive features of the CU-ID, the presence in all sessions of two teachers simultaneously from different scientific areas, as well as invitations issued to specialists on the subject of integration and to other teachers that already promote forms of integration in schools. As negative features, students noted a lack of integrated purpose, applying simultaneously the four scientific areas of the course, and also indicated the need to be familiar with more models of integrated education. Consequently, the suggestions for improvement derived from these negative features. The students also considered that their evaluation process was correct, due to the fact that it was focused on the design of an integrated project for one of the school years already mentioned.

Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication

Recent integrated circuit technologies have opened the possibility to design parallel architectures with hundreds of cores on a single chip. The design space of these parallel architectures is huge with many architectural options. Exploring the design space gets even more difficult if, beyond performance and area, we also consider extra metrics like performance and area efficiency, where the designer tries to design the architecture with the best performance per chip area and the best sustainable performance. In this paper we present an algorithm-oriented approach to design a many-core architecture. Instead of doing the design space exploration of the many core architecture based on the experimental execution results of a particular benchmark of algorithms, our approach is to make a formal analysis of the algorithms considering the main architectural aspects and to determine how each particular architectural aspect is related to the performance of the architecture when running an algorithm or set of algorithms. The architectural aspects considered include the number of cores, the local memory available in each core, the communication bandwidth between the many-core architecture and the external memory and the memory hierarchy. To exemplify the approach we did a theoretical analysis of a dense matrix multiplication algorithm and determined an equation that relates the number of execution cycles with the architectural parameters. Based on this equation a many-core architecture has been designed. The results obtained indicate that a 100 mm(2) integrated circuit design of the proposed architecture, using a 65 nm technology, is able to achieve 464 GFLOPs (double precision floating-point) for a memory bandwidth of 16 GB/s. This corresponds to a performance efficiency of 71 %. Considering a 45 nm technology, a 100 mm(2) chip attains 833 GFLOPs which corresponds to 84 % of peak performance These figures are better than those obtained by previous many-core architectures, except for the area efficiency which is limited by the lower memory bandwidth considered. The results achieved are also better than those of previous state-of-the-art many-cores architectures designed specifically to achieve high performance for matrix multiplication.

O design do manual escolar

O manual escolar, pelas suas características, é um produto de design gráfico, disciplina que tardou a desenvolver-se em Portugal. Após o 25 de Abril, as editoras escolares expandiram-se, e a globalização do ensino teve como consequência o aumento do número de manuais escolares. O desenvolvimento do design gráfico está intimamente ligado ao desenvolvimento da tecnologia informática, contribuindo fortemente para a alteração das características do manual escolar, sendo a mais notória a importância dada à imagem como portadora de informação. Sem investigação que suporte o seu actual formato, nem formação dos professores que permita explorar as suas novas potencialidades, interrogamo-nos sobre a sua eficácia. O campo da teoria da imagem é vasto e a sua aplicação, quer na realização, quer na exploração pedagógica do manual escolar, exige alguma sistematização que procuramos apresentar.

Power converter topologies for wind energy conversion systems: Integrated modeling, control strategy and performance simulation

This paper presents new integrated model for variable-speed wind energy conversion systems, considering a more accurate dynamic of the wind turbine, rotor, generator, power converter and filter. Pulse width modulation by space vector modulation associated with sliding mode is used for controlling the power converters. Also, power factor control is introduced at the output of the power converters. Comprehensive performance simulation studies are carried out with matrix, two-level and multilevel power converter topologies in order to adequately assert the system performance. Conclusions are duly drawn.

Optimal design of piezolaminated structures using B-spline strip finite element models

A package of B-spline finite strip models is developed for the linear analysis of piezolaminated plates and shells. This package is associated to a global optimization technique in order to enhance the performance of these types of structures, subjected to various types of objective functions and/or constraints, with discrete and continuous design variables. The models considered are based on a higher-order displacement field and one can apply them to the static, free vibration and buckling analyses of laminated adaptive structures with arbitrary lay-ups, loading and boundary conditions. Genetic algorithms, with either binary or floating point encoding of design variables, were considered to find optimal locations of piezoelectric actuators as well as to determine the best voltages applied to them in order to obtain a desired structure shape. These models provide an overall economy of computing effort for static and vibration problems.

Projecto e implementação de um sistema de alimentação para um transformador de alta tensão

Neste trabalho pretende-se estudar, dimensionar e implementar experimentalmente de um sistema de alimentação para transformadores de alta tensão a alta frequência. Este sistema será constituído por dois elementos principais, um rectificador monofásico em ponte totalmente controlado e por um inversor de tensão. Inicialmente realizou-se um estudo sobre as diferentes topologias possíveis para o rectificador considerando diferentes tipos de carga. Realizou-se, também, um estudo sobre o circuito de geração dos impulsos de disparo dos tiristores, executado com base num circuito integrado TCA 785, dimensionou-se os elementos constituintes do circuito de disparo, e de um sistema de controlo da tensão de saída do rectificador. Posteriormente estudou-se o funcionamento do inversor de tensão, definindo-se os modos de operação e dimensionou-se um circuito ressonante tendo em conta os parâmetros construtivos do transformador que se pretende utilizar. Finalmente procedeu-se à implementação prática dos sistemas previamente dimensionados e simulados e à apresentação dos respectivos resultados.

Projecto de um conversor redutor CC-CC comutado para SoC

A evolução da tecnologia CMOS tem possibilitado uma maior densidade de integração de circuitos tornando possível o aumento da complexidade dos sistemas. No entanto, a integração de circuitos de gestão de potência continua ainda em estudo devido à dificuldade de integrar todos os componentes. Esta solução apresenta elevadas vantagens, especialmente em aplicações electrónicas portáteis alimentadas a baterias, onde a autonomia é das principais características. No âmbito dos conversores redutores existem várias topologias de circuitos que são estudadas na área de integração. Na categoria dos conversores lineares utiliza-se o LDO (Low Dropout Regulator), apresentando no entanto baixa eficiência para relações de conversão elevadas. Os conversores comutados são elaborados através do recurso a circuitos de comutação abrupta, em que a eficiência deste tipo de conversores não depende do rácio de transformação entre a tensão de entrada e a de saída. A diminuição física dos processos CMOS tem como consequência a redução da tensão máxima que os transístores suportam, impondo o estudo de soluções tolerantes a “altatensão”, com o intuito de manter compatibilidade com tensões superiores que existam na placa onde o circuito é incluído. Os sistemas de gestão de energia são os primeiros a acompanhar esta evolução, tendo de estar aptos a fornecer a tensão que os restantes circuitos requerem. Neste trabalho é abordada uma metodologia de projecto para conversores redutores CCCC comutados em tecnologia CMOS, tendo-se maximizado a frequência com vista à integração dos componentes de filtragem em circuito integrado. A metodologia incide sobre a optimização das perdas totais inerentes à comutação e condução, dos transístores de potência e respectivos circuitos auxiliares. É apresentada uma nova metodologia para o desenvolvimento de conversores tolerantes a “alta-tensão”.

Design of a sea-level tsunami detection network for the Gulf of Cadiz

The devastating impact of the Sumatra tsunami of 26 December 2004, raised the question for scientists of how to forecast a tsunami threat. In 2005, the IOC-UNESCO XXIII assembly decided to implement a global tsunami warning system to cover the regions that were not yet protected, namely the Indian Ocean, the Caribbean and the North East Atlantic, the Mediterranean and connected seas (the NEAM region). Within NEAM, the Gulf of Cadiz is the more sensitive area, with an important record of devastating historical events. The objective of this paper is to present a preliminary design for a reliable tsunami detection network for the Gulf of Cadiz, based on a network of sea-level observatories. The tsunamigenic potential of this region has been revised in order to define the active tectonic structures. Tsunami hydrodynamic modeling and GIS technology have been used to identify the appropriate locations for the minimum number of sea-level stations. Results show that 3 tsunameters are required as the minimum number of stations necessary to assure an acceptable protection to the large coastal population in the Gulf of Cadiz. In addition, 29 tide gauge stations could be necessary to fully assess the effects of a tsunami along the affected coasts of Portugal, Spain and Morocco.

New Steel Alloys for the Design of Heat Recovery Steam Generator Components of Combined Cycle Gas Plants

Demand for power is growing every day, mainly due to emerging economies in countries such as China, Russia, India, and Brazil. During the last 50 years steam pressure and temperature in power plants have been continuously raised to improve thermal efficiency. Recent efforts to improve efficiency leads to the development of a new generation of heat recovery steam generator, where the Benson once-through technology is applied to improve the thermal efficiency. The main purpose of this paper is to analyze the mechanical behavior of a high pressure superheater manifold by applying finite element modeling and a finite element analysis with the objective of analyzing stress propagation, leading to the study of damage mechanism, e.g., uniaxial fatigue, uniaxial creep for life prediction. The objective of this paper is also to analyze the mechanical properties of the new high temperature resistant materials in the market such as 2Cr Bainitic steels (T/P23 and T/P24) and also the 9-12Cr Martensitic steels (T/P91, T/P92, E911, and P/T122). For this study the design rules for construction of power boilers to define the geometry of the HPSH manifold were applied.

Viability of Two New Mixture Design Methodologies for Self-Consolidating Concrete

This paper presents the results from an experimental study of the technical viability of two mixture designs for self-consolidating concrete (SCC) proposed by two Portuguese researchers in a previous work. The objective was to find the best method to provide the required characteristics of SCC in fresh and hardened states without having to experiment with a large number of mixtures. Five SCC mixtures, each with a volume of 25 L (6.61 gal.) were prepared using a forced mixer with a vertical axis for each of three compressive strength targets: 40, 55, and 70 MPa (5.80, 7.98, and 10.15 ksi). The mixtures' fresh state properties of fluidity, segregation resistance ability, and bleeding and blockage tendency, and their hardened state property of compressive strength were compared. For this study, the following tests were performed. slump-flow, V-funnel, L-box, box, and compressive strength. The results of this study made it possible to identify the most influential factors in the design of the SCC mixtures.