5 resultados para efficiencies

em Repositório Científico do Instituto Politécnico de Lisboa - Portugal


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Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia Mecânica

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Trabalho Final de Mestrado para obtenção do grau de mestre em Engenharia Química e Biológica

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Radio frequency (RF) energy harvesting is an emerging technology that will enable to drive the next generation of wireless sensor networks (WSNs) without the need of using batteries. In this paper, we present RF energy harvesting circuits specifically developed for GSM bands (900/1800) and a wearable dual-band antenna suitable for possible implementation within clothes for body worn applications. Besides, we address the development and experimental characterization of three different prototypes of a five-stage Dickson voltage multiplier (with match impedance circuit) responsible for harvesting the RF energy. Different printed circuit board (PCB) fabrication techniques to produce the prototypes result in different values of conversion efficiency. Therefore, we conclude that if the PCB fabrication is achieved by means of a rigorous control in the photo-positive method and chemical bath procedure applied to the PCB it allows for attaining better values for the conversion efficiency. All three prototypes (1, 2 and 3) can power supply the IRIS sensor node for RF received powers of -4 dBm, -6 dBm and -5 dBm, and conversion efficiencies of 20, 32 and 26%, respectively. © 2014 IEEE.

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Trabalho Final de Mestrado para obtenção do Grau de Mestre em Engenharia Química e Biológica

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Sparse matrix-vector multiplication (SMVM) is a fundamental operation in many scientific and engineering applications. In many cases sparse matrices have thousands of rows and columns where most of the entries are zero, while non-zero data is spread over the matrix. This sparsity of data locality reduces the effectiveness of data cache in general-purpose processors quite reducing their performance efficiency when compared to what is achieved with dense matrix multiplication. In this paper, we propose a parallel processing solution for SMVM in a many-core architecture. The architecture is tested with known benchmarks using a ZYNQ-7020 FPGA. The architecture is scalable in the number of core elements and limited only by the available memory bandwidth. It achieves performance efficiencies up to almost 70% and better performances than previous FPGA designs.