Environmental and track perturbations on multiple pantograph interaction with catenaries in high-speed trains

The top velocity of high-speed trains is generally limited by the ability to supply the proper amount of energy through the pantograph-catenary interface. The deterioration of this interaction can lead to the loss of contact, which interrupts the energy supply and originates arcing between the pantograph and the catenary, or to excessive contact forces that promote wear between the contacting elements. Another important issue is assessing on how the front pantograph influences the dynamic performance of the rear one in trainsets with two pantographs. In this work, the track and environmental conditions influence on the pantograph-catenary is addressed, with particular emphasis in the multiple pantograph operations. These studies are performed for high speed trains running at 300 km/h with relation to the separation between pantographs. Such studies contribute to identify the service conditions and the external factors influencing the contact quality on the overhead system. (C) 2013 Elsevier Ltd. All rights reserved.

Controlo directo de binário de uma máquina assíncrona trifásica

Dissertação para obtenção do grau de Mestre em Engenharia Electrotécnica Ramo de Automação e Electrónica Industrial

Avaliação de desempenho e o compromisso face ao superior hierárquico

Mestrado em Contabilidade e Gestão das Instituições Financeiras

Using dynamic reconfiguration to reduce the area of a JPEG decoder on FPGA

Partial dynamic reconfiguration of FPGAs can be used to implement complex applications using the concept of virtual hardware. In this work we have used partial dynamic reconfiguration to implement a JPEG decoder with reduced area. The image decoding process was adapted to be implemented on the FPGA fabric using this technique. The architecture was tested in a low cost ZYNQ-7020 FPGA that supports dynamic reconfiguration. The results show that the proposed solution needs only 40% of the resources utilized by a static implementation. The performance of the dynamic solution is about 9X slower than the static solution by trading-off internal resources of the FPGA. A throughput of 7 images per second is achievable with the proposed partial dynamic reconfiguration solution.