Emission of airborne ultrafine particles during welding of steel plates

The present study is focused on the characterization of ultrafine particles emitted in welding of steel using mixtures of Ar+CO2, and intends to analyze which are the main process parameters which may have influence on the emission itself. It was found that the amount of emitted ultrafine particles (measured by particle number and alveolar deposited surface area) are clearly dependent from the distance to the welding front and also from the main welding parameters, namely the current intensity and heat input in the welding process. The emission of airborne ultrafine particles seem to increase with the current intensity as fume formation rate does. When comparing the tested gas mixtures, higher emissions are observed for more oxidant mixtures, that is, mixtures with higher CO2 content, which result in higher arc stability. The later mixtures originate higher concentrations of ultrafine particles (as measured by number of particles by cm3 of air) and higher values of alveolar deposited surface area of particles, thus resulting in a more hazardous condition regarding worker's exposure. © 2014 Sociedade Portuguesa de Materiais (SPM). Published by Elsevier España, S.L. All rights reserved.

Estudo de falha em placas laminadas usando métodos analíticos e numéricos

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia de Manutenção

A many-core co-processor for embedded parallel computing on FPGA

Single processor architectures are unable to provide the required performance of high performance embedded systems. Parallel processing based on general-purpose processors can achieve these performances with a considerable increase of required resources. However, in many cases, simplified optimized parallel cores can be used instead of general-purpose processors achieving better performance at lower resource utilization. In this paper, we propose a configurable many-core architecture to serve as a co-processor for high-performance embedded computing on Field-Programmable Gate Arrays. The architecture consists of an array of configurable simple cores with support for floating-point operations interconnected with a configurable interconnection network. For each core it is possible to configure the size of the internal memory, the supported operations and number of interfacing ports. The architecture was tested in a ZYNQ-7020 FPGA in the execution of several parallel algorithms. The results show that the proposed many-core architecture achieves better performance than that achieved with a parallel generalpurpose processor and that up to 32 floating-point cores can be implemented in a ZYNQ-7020 SoC FPGA.