The effects of parental sensitivity and involvement in caregiving on mother–infant and father–infant attachment in a portuguese sample

In the present longitudinal study, we investigated attachment quality in Portuguese mother–infant and in father–infant dyads, and evaluated whether attachment quality was related to parental sensitivity during parent–infant social interaction or to the amount of time each parent spent with the infant during play and in routine caregiving activities (e.g., feeding, bathing, play). The sample consisted of 82 healthy full-term infants (30 girls, 53 boys, 48 first born), and their mothers and fathers from mostly middle-class households. To assess parental sensitivity, mothers and fathers were independently observed during free play interactions with their infants when infants were 9 and 15 months old. The videotaped interactions were scored by masked coders using the Crittenden’s CARE-Index. When infants were 12 and 18 months old, mother–infant and father–infant dyads were videotaped during an adaptation of Ainsworth’s Strange Situation. Parents also described their level of involvement in infant caregiving activities using a Portuguese version of the McBride and Mills Parent Responsibility Scale. Mothers were rated as being more sensitive than fathers during parent–infant free play at both 9 and 15 months. There also was a higher prevalence of secure attachment in mother–infant versus father–infant dyads at both 12 and 18 months. Attachment security was predicted by the amount of time mothers and fathers were involved in caregiving and play with the infant, and with parents’ behavior during parent–infant free play.

Estudo sobre a qualidade da autorregulação do bebé na situação face-to-face-still-face com o pai

Dissertação apresentada à Escola Superior de Educação de Lisboa para obtenção do grau de Mestre em Ciências da Educação Especialidade Intervenção Precoce

Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication

Recent integrated circuit technologies have opened the possibility to design parallel architectures with hundreds of cores on a single chip. The design space of these parallel architectures is huge with many architectural options. Exploring the design space gets even more difficult if, beyond performance and area, we also consider extra metrics like performance and area efficiency, where the designer tries to design the architecture with the best performance per chip area and the best sustainable performance. In this paper we present an algorithm-oriented approach to design a many-core architecture. Instead of doing the design space exploration of the many core architecture based on the experimental execution results of a particular benchmark of algorithms, our approach is to make a formal analysis of the algorithms considering the main architectural aspects and to determine how each particular architectural aspect is related to the performance of the architecture when running an algorithm or set of algorithms. The architectural aspects considered include the number of cores, the local memory available in each core, the communication bandwidth between the many-core architecture and the external memory and the memory hierarchy. To exemplify the approach we did a theoretical analysis of a dense matrix multiplication algorithm and determined an equation that relates the number of execution cycles with the architectural parameters. Based on this equation a many-core architecture has been designed. The results obtained indicate that a 100 mm(2) integrated circuit design of the proposed architecture, using a 65 nm technology, is able to achieve 464 GFLOPs (double precision floating-point) for a memory bandwidth of 16 GB/s. This corresponds to a performance efficiency of 71 %. Considering a 45 nm technology, a 100 mm(2) chip attains 833 GFLOPs which corresponds to 84 % of peak performance These figures are better than those obtained by previous many-core architectures, except for the area efficiency which is limited by the lower memory bandwidth considered. The results achieved are also better than those of previous state-of-the-art many-cores architectures designed specifically to achieve high performance for matrix multiplication.