Mathematical modelling of supercritical CO2 extraction of volatile oils from aromatic plants

The modelling of the experimental data of the extraction of the volatile oil from six aromatic plants (coriander, fennel, savoury, winter savoury, cotton lavender and thyme) was performed using five mathematical models, based on differential mass balances. In all cases the extraction was internal diffusion controlled and the internal mass transfer coefficienty (k(s)) have been found to change with pressure, temperature and particle size. For fennel, savoury and cotton lavender, the external mass transfer and the equilibrium phase also influenced the second extraction period, since k(s) changed with the tested flow rates. In general, the axial dispersion coefficient could be neglected for the conditions studied, since Peclet numbers were high. On the other hand, the solute-matrix interaction had to be considered in order to ensure a satisfactory description of the experimental data.

A biosignal embedded system for physiological computing

Thesis submitted in the fulfilment of the requirements for the Degree of Master in Electronic and Telecomunications Engineering

Many-core approach to 2D-DCT calculation using an FPGA

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia de Electrónica e Telecomunicações

A many-core co-processor for embedded parallel computing on FPGA

Single processor architectures are unable to provide the required performance of high performance embedded systems. Parallel processing based on general-purpose processors can achieve these performances with a considerable increase of required resources. However, in many cases, simplified optimized parallel cores can be used instead of general-purpose processors achieving better performance at lower resource utilization. In this paper, we propose a configurable many-core architecture to serve as a co-processor for high-performance embedded computing on Field-Programmable Gate Arrays. The architecture consists of an array of configurable simple cores with support for floating-point operations interconnected with a configurable interconnection network. For each core it is possible to configure the size of the internal memory, the supported operations and number of interfacing ports. The architecture was tested in a ZYNQ-7020 FPGA in the execution of several parallel algorithms. The results show that the proposed many-core architecture achieves better performance than that achieved with a parallel generalpurpose processor and that up to 32 floating-point cores can be implemented in a ZYNQ-7020 SoC FPGA.