222 resultados para IEEE 830
em Repositório Científico do Instituto Politécnico de Lisboa - Portugal
Resumo:
A recente norma IEEE 802.11n oferece um elevado débito em redes locais sem fios sendo por isso esperado uma adopção massiva desta tecnologia substituindo progressivamente as redes 802.11b/g. Devido à sua elevada capacidade esta recente geração de redes sem fios 802.11n permite um crescimento acentuado de serviços audiovisuais. Neste contexto esta dissertação procura estudar a rede 802.11n, caracterizando o desempenho e a qualidade associada a um serviço de transmissão de vídeo, recorrendo para o efeito a uma arquitectura de simulação da rede 802.11n. Desta forma é caracterizado o impacto das novas funcionalidades da camada MAC introduzidas na norma 801.11n, como é o caso da agregação A-MSDU e A-MPDU, bem como o impacto das novas funcionalidades da camada física como é o caso do MIMO; em ambos os casos uma optimização da parametrização é realizada. Também se verifica que as principais técnicas de codificação de vídeo H.264/AVC para optimizar o processo de distribuição de vídeo, permitem optimizar o desempenho global do sistema de transmissão. Aliando a optimização e parametrização da camada MAC, da camada física, e do processo de codificação, é possível propor um conjunto de configurações que permitem obter o melhor desempenho na qualidade de serviço da transmissão de conteúdos de vídeo numa rede 802.11n. A arquitectura de simulação construída nesta dissertação é especificamente adaptada para suportar as técnicas de agregação da camada MAC, bem como para suportar o encapsulamento em protocolos de rede que permitem a transmissão dos pacotes de vídeo RTP, codificados em H.264/AVC.
Resumo:
This paper presents the implementation of the OFDM demodulator and the Viterbi decoder, proposed as part of a wireless High Definition video receiver to be integrated in an FPGA. These blocks were implemented in a Xilinx Virtex-6 FPGA. The complete system was previously modeled and simulated using MATLAB/Simulink to extract importante hardware characteristics for the FPGA implementation.
Resumo:
We examine the instability behavior of nanocrystalline silicon (nc-Si) thin-film transistors (TFTs) in the presence of electrical and optical stress. The change in threshold voltage and sub-threshold slope is more significant under combined bias-and-light stress when compared to bias stress alone. The threshold voltage shift (Delta V-T) after 6 h of bias stress is about 7 times larger in the case with illumination than in the dark. Under bias stress alone, the primary instability mechanism is charge trapping at the semiconductor/insulator interface. In contrast, under combined bias-and-light stress, the prevailing mechanism appears to be the creation of defect states in the channel, and believed to take place in the amorphous phase, where the increase in the electron density induced by electrical bias enhances the non-radiative recombination of photo-excited electron-hole pairs. The results reported here are consistent with observations of photo-induced efficiency degradation in solar cells.
Resumo:
The concept of explaining the use of an old tool like the Smith chart, using modern tools like MATLAB [1] scripts in combination with e-learning facilities, is exemplified by two MATLAB scripts. These display, step by step, the graphical procedure that must be used to solve the double-stub impedance-matching problem. These two scripts correspond to two different possible ways to analyze this matching problem, and they are important for students to learn by themselves.
Resumo:
The intensive use of semiconductor devices enabled the development of a repetitive high-voltage pulse-generator topology from the dc voltage-multiplier (VM) concept. The proposed circuit is based on an odd VM-type circuit, where a number of dc capacitors share a common connection with different voltage ratings in each one, and the output voltage comes from a single capacitor. Standard VM rectifier and coupling diodes are used for charging the energy-storing capacitors, from an ac power supply, and two additional on/off semiconductors in each stage, to switch from the typical charging VM mode to a pulse mode with the dc energy-storing capacitors connected in series with the load. Results from a 2-kV experimental prototype with three stages, delivering a 10-mu s pulse with a 5-kHz repetition rate into a resistive load, are discussed. Additionally, the proposed circuit is compared against the solid-state Marx generator topology for the same peak input and output voltages.
Resumo:
This paper presents the Direct Power Control of Three-Phase Matrix Converters (DPC-MC) operating as Unified Power Flow Controllers (UPFC). Since matrix converters allow direct AC/AC power conversion without intermediate energy storage link, the resulting UPFC has reduced volume and cost, together with higher reliability. Theoretical principles of DPC-MC method are established based on an UPFC model, together with a new direct power control approach based on sliding mode control techniques. As a result, active and reactive power can be directly controlled by selection of an appropriate switching state of matrix converter. This new direct power control approach associated to matrix converters technology guarantees decoupled active and reactive power control, zero error tracking, fast response times and timely control actions. Simulation results show good performance of the proposed system.
Resumo:
This paper presents a new generalized solution for DC bus capacitors voltage balancing in back-to-back m level diode-clamped multilevel converters connecting AC networks. The solution is based on the DC bus average power flow and exploits the switching configuration redundancies. The proposed balancing solution is particularized for the back-to-back multilevel structure with m=5 levels. This back-to-back converter is studied working with bidirectional power flow, connecting an induction machine to the power grid.
Resumo:
This paper presents a predictive optimal matrix converter controller for a flywheel energy storage system used as Dynamic Voltage Restorer (DVR). The flywheel energy storage device is based on a steel seamless tube mounted as a vertical axis flywheel to store kinetic energy. The motor/generator is a Permanent Magnet Synchronous Machine driven by the AC-AC Matrix Converter. The matrix control method uses a discrete-time model of the converter system to predict the expected values of the input and output currents for all the 27 possible vectors generated by the matrix converter. An optimal controller minimizes control errors using a weighted cost functional. The flywheel and control process was tested as a DVR to mitigate voltage sags and swells. Simulation results show that the DVR is able to compensate the critical load voltage without delays, voltage undershoots or overshoots, overcoming the input/output coupling of matrix converters.
Resumo:
Sliding mode controllers for power converters usually employ hysteresis comparators to directly generate the power semiconductors switching states. This paper presents a new sliding mode modulator based on the direct implementation of the sliding mode stability condition, which for multilevel power converters shows advantages, as branch equalized switching frequencies and less distortion on the ac currents when operating near the rated converter power. The new sliding mode multilevel modulator is used to control a three-phase multilevel converter, operated as a reactive power compensator (STATCOM), implementing the stability condition in a digital signal processing system. The performance of this new sliding mode modulator is compared with a multilevel modulator based on hysteresis comparators. Simulation and experimental results are presented in order to highlight the system operation and control robustness.
Resumo:
Fluorescent protein microscopy imaging is nowadays one of the most important tools in biomedical research. However, the resulting images present a low signal to noise ratio and a time intensity decay due to the photobleaching effect. This phenomenon is a consequence of the decreasing on the radiation emission efficiency of the tagging protein. This occurs because the fluorophore permanently loses its ability to fluoresce, due to photochemical reactions induced by the incident light. The Poisson multiplicative noise that corrupts these images, in addition with its quality degradation due to photobleaching, make long time biological observation processes very difficult. In this paper a denoising algorithm for Poisson data, where the photobleaching effect is explicitly taken into account, is described. The algorithm is designed in a Bayesian framework where the data fidelity term models the Poisson noise generation process as well as the exponential intensity decay caused by the photobleaching. The prior term is conceived with Gibbs priors and log-Euclidean potential functions, suitable to cope with the positivity constrained nature of the parameters to be estimated. Monte Carlo tests with synthetic data are presented to characterize the performance of the algorithm. One example with real data is included to illustrate its application.
Resumo:
The big proliferation of mobile communication systems has caused an increased concern about the interaction between the human body and the antennas of mobile handsets. In order to study the problem, a multiband antenna was designed, fabricated and measured to operate over two frequency sub bands 900 and 1800 MHz. After that, we simulated the same antenna, but now, in the presence of a human head model to analyze the head's influence. First, the influence of the human head on the radiation efficiency of the antenna has been investigated as a function of the distance between the head and the antenna and with the inclination of the antenna. Furthermore, the relative amount of the electromagnetic power absorbed in the head has been obtained.
Resumo:
Implementing monolithic DC-DC converters for low power portable applications with a standard low voltage CMOS technology leads to lower production costs and higher reliability. Moreover, it allows miniaturization by the integration of two units in the same die: the power management unit that regulates the supply voltage for the second unit, a dedicated signal processor, that performs the functions required. This paper presents original techniques that limit spikes in the internal supply voltage on a monolithic DC-DC converter, extending the use of the same technology for both units. These spikes are mainly caused by fast current variations in the path connecting the external power supply to the internal pads of the converter power block. This path includes two parasitic inductances inbuilt in bond wires and in package pins. Although these parasitic inductances present relative low values when compared with the typical external inductances of DC-DC converters, their effects can not be neglected when switching high currents at high switching frequency. The associated overvoltage frequently causes destruction, reliability problems and/or control malfunction. Different spike reduction techniques are presented and compared. The proposed techniques were used in the design of the gate driver of a DC-DC converter included in a power management unit implemented in a standard 0.35 mu m CMOS technology.
Resumo:
Motion compensated frame interpolation (MCFI) is one of the most efficient solutions to generate side information (SI) in the context of distributed video coding. However, it creates SI with rather significant motion compensated errors for some frame regions while rather small for some other regions depending on the video content. In this paper, a low complexity Infra mode selection algorithm is proposed to select the most 'critical' blocks in the WZ frame and help the decoder with some reliable data for those blocks. For each block, the novel coding mode selection algorithm estimates the encoding rate for the Intra based and WZ coding modes and determines the best coding mode while maintaining a low encoder complexity. The proposed solution is evaluated in terms of rate-distortion performance with improvements up to 1.2 dB regarding a WZ coding mode only solution.
Resumo:
A newly developed solid-state repetitive high-voltage (HV) pulse modulator topology created from the mature concept of the d.c. voltage multiplier (VM) is described. The proposed circuit is based in a voltage multiplier type circuit, where a number of d.c. capacitors share a common connection with different voltage rating in each one. Hence, besides the standard VM rectifier and coupling diodes, two solid-state on/off switches are used, in each stage, to switch from the typical charging VM mode to a pulse mode with the d.c. capacitors connected in series with the load. Due to the on/off semiconductor configuration, in half-bridge structures, the maximum voltage blocked by each one is the d.c. capacitor voltage in each stage. A 2 kV prototype is described and the results are compared with PSPICE simulations.
Resumo:
O presente trabalho tem como objectivo ser um elemento de reflexão do exercício das competências de fiscalização dos Municípios, no actual contexto legal (Decreto-Lei nº 555/99 de 16 de Dezembro na redacção que lhe foi conferida pela Lei nº 60/2007 de 4 de Setembro). Este regime jurídico que visa aligeirar os procedimentos de controlo prévio das operações urbanísticas vem, numa linha inovadora, remeter para um controlo “a posteriori” o controlo administrativo das operações urbanísticas promovidas por particulares. Os limites de intervenção da Administração, num quadro em que os interesses dos particulares e o interesse público têm por vezes objectivos distintos, fazem com que a actividade de fiscalização se manifeste de alguma dificuldade. O universo deste documento abrange os municípios da Área Metropolitana de Lisboa, num total de dezoito, com uma população residente de 2.830.867 habitantes. Espera-se que as conclusões obtidas sejam dinamizadoras de melhoria futura.