FPGA implementation of IEEE 802.15.3C receiver

This paper presents the implementation of the OFDM demodulator and the Viterbi decoder, proposed as part of a wireless High Definition video receiver to be integrated in an FPGA. These blocks were implemented in a Xilinx Virtex-6 FPGA. The complete system was previously modeled and simulated using MATLAB/Simulink to extract importante hardware characteristics for the FPGA implementation.

Ferramenta computacional para medição de deslocamentos em ensaios de carga através de técnicas de processamento de imagem

Dissertação de Mestrado para a obtenção de grau de Mestre em Engenharia Eletrotécnica Ramo de Automação e Eletrónica Industrial