A high-rate mimo receiver in an FPGA

This paper describes the hardware implementation of a High-Rate MIMO Receiver in an FPGA for three modulations, namely BPSK, QPSK and 16-QAM based on the Alamouti scheme. The implementation with 16-QAM achieves more than 1.6 Gbps with 66% of the resources of a medium-sized Virtex-4 FPGA. This results indicate that the Alamouti scheme is a good design option for hardware implementation of a high-rate MIMO receiver. Also, using an FPGA, the modulation can be dynamically changed on demand.

FPGA implementation of IEEE 802.15.3C receiver

This paper presents the implementation of the OFDM demodulator and the Viterbi decoder, proposed as part of a wireless High Definition video receiver to be integrated in an FPGA. These blocks were implemented in a Xilinx Virtex-6 FPGA. The complete system was previously modeled and simulated using MATLAB/Simulink to extract importante hardware characteristics for the FPGA implementation.

Evaluation of the improvements on pharmacy technicians' work practices after implementation of operational procedures

Several antineoplasic drugs have been demonstrated to be carcinogenic or to have mutagenic and teratogenic effects. The greatest protection is achieved with the implementation of administrative and engineering controls and safety procedures. Objective: to evaluate the improvements on pharmacy technicians' work practices, after the implementation of operational procedures related to individual protection, biologic safety cabinet disinfection and cytotoxic drug preparation. Method: case-study in a hospital pharmacy undergoing a certification process. Six pharmacy technicians were observed during their daily activities. Characterization of the work practices was made using a checklist based on ISOPP and PIC guidelines. The variables studied concerning cleaning/disinfection procedures, personal protective equipment and procedures for preparing cytotoxic drugs. The same work practices were evaluated after four months of operational procedures implementation. Concordance between work practices and guidelines was considered to be a quality indicator (guidelines concordance practices number/total number of practices x 100). Results: improvements were observed after operational procedures implementation. An improvement of 6,25% in personal protective equipment practice was achieved by changing second pair of gloves every thirty minutes. The major progress, 10%, was obtained in disinfection procedure, where 80% of tasks are now realized according to guidelines.By now, we hot an improvement of only 1% at drug preparation procedure by placing one cytotoxic drug at a time inside the biological safety cabinet. Then, 85% of practices are according to guidelines. Conclusion: before operational procedures implementation 80,3% of practices were according to the guidelines, while now is 84,4%. This indicates that is necessary to review the procedures frequently in the benefit to reduce the risks associated with handling cytotoxic drugs and maintenance of drug specifications.

A Flexible Architecture for the Computation of Direct and Inverse Transforms in H.264/AVC Video Codecs

A new high throughput and scalable architecture for unified transform coding in H.264/AVC is proposed in this paper. Such flexible structure is capable of computing all the 4x4 and 2x2 transforms for Ultra High Definition Video (UHDV) applications (4320x7680@ 30fps) in real-time and with low hardware cost. These significantly high performance levels were proven with the implementation of several different configurations of the proposed structure using both FPGA and ASIC 90 nm technologies. In addition, such experimental evaluation also demonstrated the high area efficiency of theproposed architecture, which in terms of Data Throughput per Unit of Area (DTUA) is at least 1.5 times more efficient than its more prominent related designs(1).

Study on influence of the new CoDeSys V3.0 on the existing CoDeSys discipline of the Mind8 Engineering Center

CoDeSys "Controller Development Systems" is a development environment for programming in the area of automation controllers. It is an open source solution completely in line with the international industrial standard IEC 61131-3. All five programming languages for application programming as defined in IEC 61131-3 are available in the development environment. These features give professionals greater flexibility with regard to programming and allow control engineers have the ability to program for many different applications in the languages in which they feel most comfortable. Over 200 manufacturers of devices from different industrial sectors offer intelligent automation devices with a CoDeSys programming interface. In 2006, version 3 was released with new updates and tools. One of the great innovations of the new version of CoDeSys is object oriented programming. Object oriented programming (OOP) offers great advantages to the user for example when wanting to reuse existing parts of the application or when working on one application with several developers. For this reuse can be prepared a source code with several well known parts and this is automatically generated where necessary in a project, users can improve then the time/cost/quality management. Until now in version 2 it was necessary to have hardware interface called “Eni-Server” to have access to the generated XML code. Another of the novelties of the new version is a tool called Export PLCopenXML. This tool makes it possible to export the open XML code without the need of specific hardware. This type of code has own requisites to be able to comply with the standard described above. With XML code and with the knowledge how it works it is possible to do component-oriented development of machines with modular programming in an easy way. Eplan Engineering Center (EEC) is a software tool developed by Mind8 GmbH & Co. KG that allows configuring and generating automation projects. Therefore it uses modules of PLC code. The EEC already has a library to generate code for CoDeSys version 2. For version 3 and the constant innovation of drivers by manufacturers, it is necessary to implement a new library in this software. Therefore it is important to study the XML export to be then able to design any type of machine. The purpose of this master thesis is to study the new version of the CoDeSys XML taking into account all aspects and impact on the existing CoDeSys V2 models and libraries in the company Harro Höfliger Verpackungsmaschinen GmbH. For achieve this goal a small sample named “Traffic light” in CoDeSys version 2 will be done and then, using the tools of the new version it there will be a project with version 3 and also the EEC implementation for the automatically generated code.

Implementation of proton therapy in the portuguese context of radiotherapy

Cancer is a national and international health care concern. It’s important to find strategies for early diagnosis as well as for the optimization of the various therapeutic options currently existing in Portugal. Cancer is the second leading cause of death in Portugal, the choice of this study, is due to the importance of radiotherapy approach in cancer treatment and because is the therapy used in 40% of oncology patients. Radiation therapy has evolve data technological level, that allows new treatment techniques that are more efficient and that also promotes greater professional satisfaction. The hadrons are charged particles, used in cancer therapy. These particles can bring a paradigm shift regarding the therapeutic approach in radiotherapy. The technique used is proton therapy, that reveal to be more accurate, efficacious and less toxic to surrounding tissue. Proton therapy may be a promising development in the field of oncology and how the treatment is given in radiotherapy. Although there is awareness of the benefits of proton therapy in oncology it’s also important to take in consideration the costs of these therapy, because they are considerably higher than conventional treatments of radiotherapy. Given the lack of a proton therapy service in Portugal, this study aims to be a documentary analysis of clinical records that will achieve the following objectives: to identify the number of cancer patients diagnosed in 2010 in Portugal and to calculate the estimated number of patients that could have been treated with proton therapy according to the Health Council of the Netherlands registration document.

A 5GHz1.8V Low Power CMOS Low-Noise Amplifier

Wireless local-area networks (WLANs) have been deployed as office and home communications infrastructures worldwide. The diversification of the standards, such as IEEE 802.11 series demands the design of RF front-ends. Low power consumption is one of the most important design concerns in the application of those technologies. To maintain competitive hardware costs, CMOS has been used since it is the best solution for low cost and high integration processing, allowing analog circuits to be mixed with digital ones. In the receiver chain, the low noise amplifier (LNA) is one of the most critical blocks in a transceiver design. The sensitivity is mainly determined by the LNA noise figure and gain. It interfaces with the pre-select filter and the mixer. Furthermore, since it is the first gain stage, care must be taken to provide accurate input match, low-noise figure, good linearity and a sufficient gain over a wide band of operation. Several CMOS LNAs have been reported during the last decade, showing that the most research has been done at 802.11/b and GSM standards (900-2400MHz spectrum) and more recently at 802.11/a (5GHz band). One of the more significant disadvantages of 802.11/b is that the frequency band is crowded and subject to interference from other technologies, as is 2.4GHz cordless phones and Bluetooth. As the demand for radio-frequency integrated circuits, operating at higher frequency bands, increases, the IEEE 802.11/a standard becomes a very attractive option to wireless communication system developers. This paper presents the design and implementation of a low power, low noise amplifier aimed at IEEE 802.11a for WLAN applications. It was designed to be integrated with an active balun and mixer, representing the first step toward a fully integrated monolithic WLAN receiver. All the required circuits are integrated at the same die and are powered by 1.8V supply source. Preliminary experimental results (S-parameters) are shown and promise excellent results. The LNA circuit design details are illustrated in Section 2. Spectre simulation results focused at gain, noise figure (NF) and input/output matching are presented in Section 3. Finally, conclusions and comparison with other recently reported LNAs are made in Section 4, followed by future work.

A 802.11p prototype implementation

This paper presents an IEEE 802.11p full-stack prototype implementation to data exchange among vehicles and between vehicles and the roadway infrastructures. The prototype architecture is based on FPGAs for Intermediate Frequency (IF) and base band purposes, using 802.11a based transceivers for RF interfaces. Power amplifiers were also addressed, by using commercial and in-house solutions. This implementation aims to provide technical solutions for Intelligent Transportation Systems (ITS) field, namely for tolling and traffic management related services, in order to promote safety, mobility and driving comfort through the dynamic and real-time cooperation among vehicles and/or between vehicles and infrastructures. The performance of the proposed scheme is tested under realistic urban and suburban driving conditions. Preliminary results are promising, since they comply with most of the 802.11p standard requirements.

Implementation of thr INSPIRE Directive on road infrastructure in Portugal

Prémio - CEN/TC 287 AWARD FOR EXCELLENCE IN INSIRE 2012 Implementation of the INSPIRE Directive on Road Infrastructure in Portugal Inês Soares, aluna de Mestrado em engenharia civil do ISEL, Instituto Superior de Engenharia de Lisboa e Paulo Martins, e o seu orientador, receberam um prémio europeu, no dia 27 de junho, em Istambul na Turquia, numa conferência internacional organizada pela Comissão Europeia e pelo governo Turco.  A jovem portuguesa foi escolhida entre cerca de 20 candidatos de vários países. Paulo Matos Martins, professor no ISEL, além de mentor do trabalho premiado, foi orientador de mestrado da aluna e explica que se trata de um estudo sobre a aplicação da Diretiva comunitária INSPIRE à infraestrutura rodoviária nacional que contou com a estreita colaboração do InIR, Instituto da Infraestrutura Rodoviária através da coorientação da engenheira Adelaide Costa e colaboração técnica do engenheiro Rui Luso Soares.  O projeto-piloto correspondeu à criação de uma aplicação informática que permite aceder a informação geográfica harmonizada relativa à infraestrutura rodoviária nacional, de acordo com as disposições de execução INSPIRE, dando cumprimento aos requisitos impostos pela Diretiva às entidades responsáveis por este tipo de informação, entre as quais se incluem diversos organismos públicos (podendo no futuro vir a incluir as autarquias), permitindo aos decisores políticos e a todos os cidadãos o fácil acesso a informação de qualidade sobre as infraestruturas, o território e o ambiente. 

Parallel implementation of vertex component analysis for hyperspectral endmember extraction

International Conference with Peer Review 2012 IEEE International Conference in Geoscience and Remote Sensing Symposium (IGARSS), 22-27 July 2012, Munich, Germany

Automatic synthesis of VHDL Hardware Components from IOPT Petri Net models

Conferência: 39th Annual Conference of the IEEE Industrial-Electronics-Society (IECON), Vienna, Austria, Nov 10-14, 2013

Implementação em hardware reconfigurável de método de separação de dados hiperespetrais

Relatório do Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia de Electrónica e Telecomunicações

Simulação de plataformas para dispositivos móveis: infraestrutura de simulação sensorial para android

Projeto para obtenção do grau de Mestre em Engenharia Informática e de Computadores

Sistema de reconhecimento de impressões digitais baseado em FPGA

Trabalho de Projeto para obtenção do grau de Mestre em Engenharia de Eletrónica e Telecomunicações

Efficient Implementation Of A Single-Precision Floating-Point Arithmetic Unit on FPGA

This paper presents a single precision floating point arithmetic unit with support for multiplication, addition, fused multiply-add, reciprocal, square-root and inverse squareroot with high-performance and low resource usage. The design uses a piecewise 2nd order polynomial approximation to implement reciprocal, square-root and inverse square-root. The unit can be configured with any number of operations and is capable to calculate any function with a throughput of one operation per cycle. The floatingpoint multiplier of the unit is also used to implement the polynomial approximation and the fused multiply-add operation. We have compared our implementation with other state-of-the-art proposals, including the Xilinx Core-Gen operators, and conclude that the approach has a high relative performance/area efficiency. © 2014 Technical University of Munich (TUM).