FPGA implementation of IEEE 802.15.3C receiver

This paper presents the implementation of the OFDM demodulator and the Viterbi decoder, proposed as part of a wireless High Definition video receiver to be integrated in an FPGA. These blocks were implemented in a Xilinx Virtex-6 FPGA. The complete system was previously modeled and simulated using MATLAB/Simulink to extract importante hardware characteristics for the FPGA implementation.

Antenas cornetas para o satélite CosmoGal

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia Electrónica e Telecomunicações

Sistema de climatização para um edifício da Rede de Energia Nacional

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia Mecânica

Planning smart cities using wireless low energy monitoring systems

Thesis to obtain the Master Degree in Electronics and Telecommunications Engineering