A CMOS micro power switched-capacitor DC-DC step-up converter for indoor light energy harvesting applications

This paper presents a micro power light energy harvesting system for indoor environments. Light energy is collected by amorphous silicon photovoltaic (a-Si:H PV) cells, processed by a switched capacitor (SC) voltage doubler circuit with maximum power point tracking (MPPT), and finally stored in a large capacitor. The MPPT fractional open circuit voltage (V-OC) technique is implemented by an asynchronous state machine (ASM) that creates and dynamically adjusts the clock frequency of the step-up SC circuit, matching the input impedance of the SC circuit to the maximum power point condition of the PV cells. The ASM has a separate local power supply to make it robust against load variations. In order to reduce the area occupied by the SC circuit, while maintaining an acceptable efficiency value, the SC circuit uses MOSFET capacitors with a charge sharing scheme for the bottom plate parasitic capacitors. The circuit occupies an area of 0.31 mm(2) in a 130 nm CMOS technology. The system was designed in order to work under realistic indoor light intensities. Experimental results show that the proposed system, using PV cells with an area of 14 cm(2), is capable of starting-up from a 0 V condition, with an irradiance of only 0.32 W/m(2). After starting-up, the system requires an irradiance of only 0.18 W/m(2) (18 mu W/cm(2)) to remain operating. The ASM circuit can operate correctly using a local power supply voltage of 453 mV, dissipating only 0.085 mu W. These values are, to the best of the authors' knowledge, the lowest reported in the literature. The maximum efficiency of the SC converter is 70.3 % for an input power of 48 mu W, which is comparable with reported values from circuits operating at similar power levels.

Experimental Study And Evaluation Of Paper-Based Inkjet Electrodes For ECG Signal Acquisition

Applications involving biosignals, such as Electrocardiography (ECG), are becoming more pervasive with the extension towards non-intrusive scenarios helping targeting ambulatory healthcare monitoring, emotion assessment, among many others. In this study we introduce a new type of silver/silver chloride (Ag/AgCl) electrodes based on a paper substrate and produced using an inkjet printing technique. This type of electrodes can increase the potential applications of biosignal acquisition technologies for everyday life use, given that there are several advantages, such as cost reduction and easier recycling, resultant from the approach explored in our work. We performed a comparison study to assess the quality of this new electrode type, in which ECG data was collected with three types of Ag/AgCl electrodes: i) gelled; ii) dry iii) paper-based inkjet printed. We also compared the performance of each electrode when acquired using a professional-grade gold standard device, and a low cost platform. Experimental results showed that data acquired using our proposed inkjet printed electrode is highly correlated with data obtained through conventional electrodes. Moreover, the electrodes are robust to high-end and low-end data acquisition devices. Copyright © 2014 SCITEPRESS - Science and Technology Publications. All rights reserved.

The evolution of user mobility on the Eduroam network

The emergence of smartphones with Wireless LAN (WiFi) network interfaces brought new challenges to application developers. The expected increase of users connectivity will impact their expectations for example on the performance of background applications. Unfortunately, the number and breadth of the studies on the new patterns of user mobility and connectivity that result from the emergence of smartphones is still insufficient to support this claim. This paper contributes with preliminary results on a large scale study of the usage pattern of about 49000 devices and 31000 users who accessed at least one access point of the eduroam WiFi network on the campuses of the Lisbon Polytechnic Institute. Results confirm that the increasing number of smartphones resulted in significant changes to the pattern of use, with impact on the amount of traffic and users connection time.

Trends Of CPU, GPU and FPGA for high-performance computing

Floating-point computing with more than one TFLOP of peak performance is already a reality in recent Field-Programmable Gate Arrays (FPGA). General-Purpose Graphics Processing Units (GPGPU) and recent many-core CPUs have also taken advantage of the recent technological innovations in integrated circuit (IC) design and had also dramatically improved their peak performances. In this paper, we compare the trends of these computing architectures for high-performance computing and survey these platforms in the execution of algorithms belonging to different scientific application domains. Trends in peak performance, power consumption and sustained performances, for particular applications, show that FPGAs are increasing the gap to GPUs and many-core CPUs moving them away from high-performance computing with intensive floating-point calculations. FPGAs become competitive for custom floating-point or fixed-point representations, for smaller input sizes of certain algorithms, for combinational logic problems and parallel map-reduce problems. © 2014 Technical University of Munich (TUM).

A perturbation and observation routine used to control a power converter

This paper presents a programable perturbation and observation control implementation for a wind generation system and its power electronic converter. The objective of the method in this particular application is to adjust the power delivered to charge a battery to its maximum and allowable value, function of the real values of several parameters and their continuous variation, the most important the wind velocity and the turbine efficiency. Also, to improve the power throughput and to use the turbine and generator marginal zones of operation, an unusual power converter is used, allowing a wide range for the input voltage values. The implemented control is continuously measuring the actual power and looks for a new and powerful operation point. © 2014 IEEE.

An internet remote laboratory to teach industrial automation

This paper presents the new internet remote laboratory (IRL), constructed at Mechanical Engineering Department (MED), Instituto Superior de Engenharia de Lisboa (ISEL), to teach Industrial Automation, namely electropneumatic cycles. The aim of this work was the development and implementation of a remote laboratory that was simple and effective from the user point of view, allowing access to all its functionalities through a web browser without having to install any other program and giving access to all the features that the students can find at the physical laboratory. With this goal in mind, it has been implemented a simple architecture with the new programmable logic controller (PLC) SIEMENS S7-1200, and with the aid of several free programs, programming technologies such as JavaScript, PHP and databases, it was possible to have a remote laboratory, with a simple interface, to teach industrial automation students.

Big Bang bifurcations and allee effect in Blumberg’s dynamics

This paper concerns dynamics and bifurcations properties of a class of continuous-defined one-dimensional maps, in a three-dimensional parameter space: Blumberg's functions. This family of functions naturally incorporates a major focus of ecological research: the Allee effect. We provide a necessary condition for the occurrence of this phenomenon, associated with the stability of a fixed point. A central point of our investigation is the study of bifurcations structure for this class of functions. We verified that under some sufficient conditions, Blumberg's functions have a particular bifurcations structure: the big bang bifurcations of the so-called "box-within-a-box" type, but for different kinds of boxes. Moreover, it is verified that these bifurcation cascades converge to different big bang bifurcation curves, where for the corresponding parameter values are associated distinct attractors. This work contributes to clarify the big bang bifurcation analysis for continuous maps. To support our results, we present fold and flip bifurcations curves and surfaces, and numerical simulations of several bifurcation diagrams.

Relevância da assertividade na comunicação profissional de saúde-paciente

Actualmente existem evidências suficientes sobre os problemas de comunicação entre profissionais de saúde e pacientes e os benefícios de uma comunicação eficaz. Alguns autores chegam mesmo a considerar a comunicação como a ferramenta mais importante nos cuidados de saúde. Desde o início dos anos 90, as escolas médicas têm aumentado o interesse no ensino de competências comunicacionais; contudo, e não obstante este interesse crescente, a comunicação assertiva parece ser votada ao esquecimento. Na verdade, enquanto a assertividade tem recebido atenção crescente na literatura da Psicologia, os profissionais de saúde têm-se mostrado relutantes em aderir a esta área do saber, sendo os treinos assertivos para cuidadores ainda muito escassos. O objectivo deste trabalho é apresentar uma visão geral da assertividade e dos contributos desta para a comunicação eficaz dos profissionais de saúde com os pacientes e apontar seis temáticas específicas (por exemplo, lidar com reacções emocionais excessivas; elaborar pedidos) que devem integrar os treinos de comunicação para estudantes da área da saúde e profissionais de saúde.

Evolução do crédito concedido e vencido em Portugal, por setores de atividade, no período de 2008 a 2012

Mestrado em Contabilidade e Gestão das Instituições Financeiras

Performance assessment of a wind energy conversion system using a hierarchical controller structure

This paper deals with a hierarchical structure composed by an event-based supervisor in a higher level and two distinct proportional integral (PI) controllers in a lower level. The controllers are applied to a variable speed wind energy conversion system with doubly-fed induction generator, namely, the fuzzy PI control and the fractional-order PI control. The event-based supervisor analyses the operation state of the wind energy conversion system among four possible operational states: park, start-up, generating or brake and sends the operation state to the controllers in the lower level. In start-up state, the controllers only act on electric torque while pitch angle is equal to zero. In generating state, the controllers must act on the pitch angle of the blades in order to maintain the electric power around the nominal value, thus ensuring that the safety conditions required for integration in the electric grid are met. Comparisons between fuzzy PI and fractional-order PI pitch controllers applied to a wind turbine benchmark model are given and simulation results by Matlab/Simulink are shown. From the results regarding the closed loop point of view, fuzzy PI controller allows a smoother response at the expense of larger number of variations of the pitch angle, implying frequent switches between operational states. On the other hand fractional-order PI controller allows an oscillatory response with less control effort, reducing switches between operational states. (C) 2015 Elsevier Ltd. All rights reserved.

Simulation of rectifier voltage malfunction on OWECS, four-level converter, HVDC light link: Smart grid context tool

This paper presents a model for the simulation of an offshore wind system having a rectifier input voltage malfunction at one phase. The offshore wind system model comprises a variable-speed wind turbine supported on a floating platform, equipped with a permanent magnet synchronous generator using full-power four-level neutral point clamped converter. The link from the offshore floating platform to the onshore electrical grid is done through a light high voltage direct current submarine cable. The drive train is modeled by a three-mass model. Considerations about the smart grid context are offered for the use of the model in such a context. The rectifier voltage malfunction domino effect is presented as a case study to show capabilities of the model. (C) 2015 Elsevier Ltd. All rights reserved.

Algorithm-oriented design of efficient many-core architectures applied to dense matrix multiplication

Recent integrated circuit technologies have opened the possibility to design parallel architectures with hundreds of cores on a single chip. The design space of these parallel architectures is huge with many architectural options. Exploring the design space gets even more difficult if, beyond performance and area, we also consider extra metrics like performance and area efficiency, where the designer tries to design the architecture with the best performance per chip area and the best sustainable performance. In this paper we present an algorithm-oriented approach to design a many-core architecture. Instead of doing the design space exploration of the many core architecture based on the experimental execution results of a particular benchmark of algorithms, our approach is to make a formal analysis of the algorithms considering the main architectural aspects and to determine how each particular architectural aspect is related to the performance of the architecture when running an algorithm or set of algorithms. The architectural aspects considered include the number of cores, the local memory available in each core, the communication bandwidth between the many-core architecture and the external memory and the memory hierarchy. To exemplify the approach we did a theoretical analysis of a dense matrix multiplication algorithm and determined an equation that relates the number of execution cycles with the architectural parameters. Based on this equation a many-core architecture has been designed. The results obtained indicate that a 100 mm(2) integrated circuit design of the proposed architecture, using a 65 nm technology, is able to achieve 464 GFLOPs (double precision floating-point) for a memory bandwidth of 16 GB/s. This corresponds to a performance efficiency of 71 %. Considering a 45 nm technology, a 100 mm(2) chip attains 833 GFLOPs which corresponds to 84 % of peak performance These figures are better than those obtained by previous many-core architectures, except for the area efficiency which is limited by the lower memory bandwidth considered. The results achieved are also better than those of previous state-of-the-art many-cores architectures designed specifically to achieve high performance for matrix multiplication.

Detect and pointing algorithm's performance for a planar smart antenna array: a review

An adaptive antenna array combines the signal of each element, using some constraints to produce the radiation pattern of the antenna, while maximizing the performance of the system. Direction of arrival (DOA) algorithms are applied to determine the directions of impinging signals, whereas beamforming techniques are employed to determine the appropriate weights for the array elements, to create the desired pattern. In this paper, a detailed analysis of both categories of algorithms is made, when a planar antenna array is used. Several simulation results show that it is possible to point an antenna array in a desired direction based on the DOA estimation and on the beamforming algorithms. A comparison of the performance in terms of runtime and accuracy of the used algorithms is made. These characteristics are dependent on the SNR of the incoming signal.

Análise sísmica e proposta de reforço de uma estrutura do séc. XIX sujeita a uma reabilitação parcial

Trabalho final de Mestrado para a obtenção do grau de mestre em Engenharia Civil

A many-core co-processor for embedded parallel computing on FPGA

Single processor architectures are unable to provide the required performance of high performance embedded systems. Parallel processing based on general-purpose processors can achieve these performances with a considerable increase of required resources. However, in many cases, simplified optimized parallel cores can be used instead of general-purpose processors achieving better performance at lower resource utilization. In this paper, we propose a configurable many-core architecture to serve as a co-processor for high-performance embedded computing on Field-Programmable Gate Arrays. The architecture consists of an array of configurable simple cores with support for floating-point operations interconnected with a configurable interconnection network. For each core it is possible to configure the size of the internal memory, the supported operations and number of interfacing ports. The architecture was tested in a ZYNQ-7020 FPGA in the execution of several parallel algorithms. The results show that the proposed many-core architecture achieves better performance than that achieved with a parallel generalpurpose processor and that up to 32 floating-point cores can be implemented in a ZYNQ-7020 SoC FPGA.