Avaliação da implementação de programa de fiabilidade de aeronaves na Força Aérea Portuguesa

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia Mecânica

Comparison of deposited surface area of airbone ultrafine particles generated from two welding processes

This article describes work performed on the assessment of the levels of airborne ultrafine particles emitted in two welding processes metal-active gas (MAG) of carbon steel and friction-stir welding (FSW) of aluminium in terms of deposited area in alveolar tract of the lung using a nanoparticle surface area monitor analyser. The obtained results showed the dependence from process parameters on emitted ultrafine particles and clearly demonstrated the presence of ultrafine particles, when compared with background levels. The obtained results showed that the process that results on the lower levels of alveolar-deposited surface area is FSW, unlike MAG. Nevertheless, all the tested processes resulted in important doses of ultrafine particles that are to be deposited in the human lung of exposed workers.

Projecto de execução do centro comercial Mercado da Praia: Cidade da Praia: Cabo Verde

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia Civil

A Força Aérea Portuguesa e o voo nas redes sociais

Trabalho de projeto apresentado à Escola Superior de Comunicação Social como parte dos requisitos para obtenção de grau de mestre em Publicidade e Marketing.

Using dynamic reconfiguration to reduce the area of a JPEG decoder on FPGA

Partial dynamic reconfiguration of FPGAs can be used to implement complex applications using the concept of virtual hardware. In this work we have used partial dynamic reconfiguration to implement a JPEG decoder with reduced area. The image decoding process was adapted to be implemented on the FPGA fabric using this technique. The architecture was tested in a low cost ZYNQ-7020 FPGA that supports dynamic reconfiguration. The results show that the proposed solution needs only 40% of the resources utilized by a static implementation. The performance of the dynamic solution is about 9X slower than the static solution by trading-off internal resources of the FPGA. A throughput of 7 images per second is achievable with the proposed partial dynamic reconfiguration solution.