91 resultados para Engineering Physics


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Twelve samples with different grain sizes were prepared by normal grain growth and by primary recrystallization, and the hysteresis dissipated energy was measured by a quasi-static method. Results showed a linear relation between hysteresis energy loss and the inverse of grain size, which is here called Mager`s law, for maximum inductions from 0.6 to 1.5 T, and a Steinmetz power law relation between hysteresis loss and maximum induction for all samples. The combined effect is better described by a Mager`s law where the coefficients follow Steinmetz law.

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A duplex surface treatment consisting of High Temperature Gas Nitriding (HTGN) followed by Low Temperature Plasma Nitriding (LTPN) was carried out in an UNS S31803 duplex stainless steel. The HTGN treatment was intended to produce a relatively thick and hard fully austenitic layer giving mechanical support to the thinner and much harder expanded austenite layer. HTGN was performed at 1200 degrees C for 3 h, in a 0.1 MPa N(2) atmosphere while LTPN, was carried out in a 75% N(2) + 25% H(2) atmosphere, at 400 degrees C for 12 h, under a 250 Pa pressure, and 450 V. An expanded austenite gamma(N) layer, 2.3 mu m thick, 1500 HVO.025 hard, was formed on top of a 100 mu m thick, 330 HV 0.1 hard, fully austenitic layer, containing 0.9 wt% N. For comparison purposes LTPN was carried out with UNS S30403 stainless steel specimens obtaining a 4.0 mu m thick, 1500 HV 0.025 hard, expanded austenite layer formed on top of a fully austenitic matrix having 190 HV 0.1. The nitrided specimens were tested in a 20 kHz vibratory cavitation-erosion testing equipment. Comparison between the duplex treated UNS S31803 steel and the low temperature plasma nitrided UNS S30403 steel, resulted in incubation times almost 9 times greater. The maximum cavitation wear rate of the LTPN UNS S30403 was 5.5 g/m(2)h, 180 times greater than the one measured for the duplex treated UNS S31803 steel. The greater cavitation wear resistance of the duplex treated UNS S31803 steel, compared to the LTPN treated UNS S30403 steel was explained by the greater mechanical support the fully austenitic, 330 HV 0.1 hard, 100 mu m layer gives to the expanded austenite layer formed on top of the specimen after LTPN. A strong crystallographic textured surface, inherited from the fully austenitic layer formed during HTGN, with the expanded austenite layer showing {101} crystallographic planes//surface contributed also to improve the cavitation resistance of the duplex treated steel. (C) 2010 Elsevier B.V. All rights reserved.

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To explain the magnetic behavior of plastic deformation of thin magnetic films (Fe and permalloy) on an elastic substrate (nitinol), it is noted that unlike in the bulk, the dislocation density does not increase dramatically because of the dimensional constraint. As a result, the resulting residual stress, even though strain hardening is limited, dominates the observed magnetic behavior. Thus, with the field parallel to the stress axis, the compressive residual stress resulting from plastic deformation causes a decrease in remanence and an increase in coercivity; and with the field perpendicular to the stress axis, the resulting compressive residual stress causes an increase in remanence and a decrease in coercivity. These elements have been inserted into the model previously developed for plastic deformation in the bulk, producing the aforementioned behavior, which has been observed experimentally in the films.

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Before one models the effect of plastic deformation on magnetoacoustic emission (MAE), one must first treat non-180 degrees domain wall motion. In this paper, we take the Alessandro-Beatrice-Bertotti-Montorsi (ABBM) model and modify it to treat non-180 degrees wall motion. We then insert a modified stress-dependent Jiles-Atherton model, which treats plastic deformation, into the modified ABBM model to treat MAE and magnetic Barkhausen noise (HBN). In fitting the dependence of these quantities on plastic deformation, we apply a model for when deformation gets into the stage where dislocation tangles are formed, noting two chief effects, one due to increased density of emission centers owing to increased dislocation density, and the other due to a more gentle increase in the residual stress in the vicinity of the dislocation tangles as deformation is increased.

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This paper presents the results of the in-depth study of the Barkhausen effect signal properties for the plastically deformed Fe-2%Si samples. The investigated samples have been deformed by cold rolling up to plastic strain epsilon(p) = 8%. The first approach consisted of time-domain-resolved pulse and frequency analysis of the Barkhausen noise signals whereas the complementary study consisted of the time-resolved pulse count analysis as well as a total pulse count. The latter included determination of time distribution of pulses for different threshold voltage levels as well as the total pulse count as a function of both the amplitude and the duration time of the pulses. The obtained results suggest that the observed increase in the Barkhausen noise signal intensity as a function of deformation level is mainly due to the increase in the number of bigger pulses.

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This work describes the development of an engineering approach based upon a toughness scaling methodology incorporating the effects of weld strength mismatch on crack-tip driving forces. The approach adopts a nondimensional Weibull stress, (sigma) over bar (w), as a the near-tip driving force to correlate cleavage fracture across cracked weld configurations with different mismatch conditions even though the loading parameter (measured by J) may vary widely due to mismatch and constraint variations. Application of the procedure to predict the failure strain for an overmatch girth weld made of an API X80 pipeline steel demonstrates the effectiveness of the micromechanics approach. Overall, the results lend strong support to use a Weibull stress based procedure in defect assessments of structural welds.

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The impact of the titanium nitride (TIN) gate electrode thickness has been investigated in n and p channel SOI multiple gate field effect transistors (MuGFETs) through low frequency noise charge pumping and static measurements as well as capacitance-voltage curves The results suggest that a thicker TIN metal gate electrode gives rise to a higher EOT a lower mobility and a higher interface trap density The devices have also been studied for different back gate biases where the GIFBE onset occurs at lower front-gate voltage for thinner TIN metal gate thickness and at higher V(GF) In addition it is demonstrated that post deposition nitridation of the MOCVD HfSiO gate dielectric exhibits an unexpected trend with TIN gate electrode thickness where a continuous variation of EOT and an increase on the degradation of the interface quality are observed (C) 2010 Elsevier Ltd All rights reserved

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The harmonic distortion (HD) exhibited by un-strained and biaxially strained fin-shaped field-effect transistors operating in saturation as single-transistor amplifiers has been investigated for devices with different channel lengths L and fin widths W(fin). The study has been performed through device characterization, 3-D device simulations, and modeling. Nonlinearity has been evaluated in terms of second- and third-order HDs (HD2 and HD3, respectively), and a discussion on its physical sources has been carried out. Also, the influence of the open-loop voltage gain AV in HD has been observed.

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This paper is a study of various electric signals, which have been employed throughout the history of communication engineering in its two main landmarks: the telegraph and the telephone. The signals are presented in their time and frequency domain representations. The historical order has been followed in the presentation: wired systems, spark gap wireless, continuous wave (CW) and amplitude modulation (AM), detection by rectification, and frequency modulation (FM). The analysis of these signals is meant to lead into a better understanding of the evolution of communication technology. The material presented in this work could be used to illustrate ""Signals and Systems"" and ""Communication Systems"" courses by taking advantage of its technical as well as historical contents.

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The theoretical and experimental open-circuit voltage optimizations of a simple fabrication process of silicon solar cells n(+)p with rear passivation are presented. The theoretical results were obtained by using an in-house developed program, including the light trapping effect and metal-grid optimization. On the other hand, the experimental steps were monitored by the photoconductive decay technique. The starting materials presented thickness of about 300 pm and resistivities: FZ (0.5 Omega cm), Cz-type 1 (2.5 Omega cm) and Cz-type 2 (3.3 Omega cm). The Gaussian profile emitters were optimized with sheet resistance between 55 Omega/sq and 100 Omega/sq, and approximately 2.0 mu m thickness in accordance to the theoretical results. Excellent implied open-circuit voltages of 670.8 mV, 652.5 mV and 662.6 mV, for FZ, Cz-type 1 and Cz-type 2 silicon wafers, respectively, could be associated to the measured lifetimes that represents solar cell efficiency up to 20% if a low cost anti-reflection coating system, composed by random pyramids and SiO(2) layer, is considered even for typical Cz silicon. (C) 2009 Elsevier Ltd. All rights reserved.

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The trapezium is often a better approximation for the FinFET cross-section shape, rather than the design-intended rectangle. The frequent width variations along the vertical direction, caused by the etching process that is used for fin definition, may imply in inclined sidewalls and the inclination angles can vary in a significant range. These geometric variations may cause some important changes in the device electrical characteristics. This work analyzes the influence of the FinFET sidewall inclination angle on some relevant parameters for analog design, such as threshold voltage, output conductance, transconductance, intrinsic voltage gain (A V), gate capacitance and unit-gain frequency, through 3D numeric simulation. The intrinsic gain is affected by alterations in transconductance and output conductance. The results show that both parameters depend on the shape, but in different ways. Transconductance depends mainly on the sidewall inclination angle and the fixed average fin width, whereas the output conductance depends mainly on the average fin width and is weakly dependent on the sidewall inclination angle. The simulation results also show that higher voltage gains are obtained for smaller average fin widths with inclination angles that correspond to inverted trapeziums, i.e. for shapes where the channel width is larger at the top than at the transistor base because of the higher attained transconductance. When the channel top is thinner than the base, the transconductance degradation affects the intrinsic voltage gain. The total gate capacitances also present behavior dependent on the sidewall angle, with higher values for inverted trapezium shapes and, as a consequence, lower unit-gain frequencies.

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This work characterizes the analog performance of SOI n-MuGFETs with HfSiO gate dielectric and TiN metal gate with respect to the influence of the high-k post-nitridation. TiN thickness and device rotation. A thinner TiN metal gate is found favorable for improved analog characteristics showing an increase in intrinsic voltage gain. The devices where the high-k material is subjected to a nitridation step indicated a degradation of the Early voltage (V(EA)) values which resulted in a lower voltage gain. The 45 degrees rotated devices have a smaller V(EA) than the standard ones when a HfSiO dielectric is used. However, the higher transconductance of these devices, due to the increased mobility in the (1 0 0) sidewall orientation, compensates this V(EA) degradation of the voltage gain, keeping it nearly equal to the voltage gain values of the standard devices. (C) 2011 Elsevier Ltd. All rights reserved.

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The multiple-gate field-effect transistor (MuGFET) is a device with a gate folded on different sides of the channel region. They are one of the most promising technological solutions to create high-performance ultra-scaled SOI CMOS. In this work, the behavior of the threshold voltage in double-gate, triple-gate and quadruple-gate SOI transistors with different channel doping concentrations is studied through three-dimensional numerical simulation. The results indicated that for double-gate transistors, one or two threshold voltages can be observed, depending on the channel doping concentration. However, in triple-gate and quadruple-gate it is possible to observe up to four threshold voltages due to the corner effect and the different doping concentration between the top and bottom of the Fin. (C) 2008 Elsevier Ltd. All rights reserved.

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This work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-K dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is demonstrated that both standard and strained FinFETs with short channel length and narrow fins have similar analog properties, whereas the increase of the channel length degrades the early voltage of the strained devices, consequently decreasing the device intrinsic voltage gain with respect to standard ones. Narrow strained FinFETs with long channel show a degradation of the Early voltage if compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect. (C) 2008 Elsevier Ltd. All rights reserved.

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This work proposes a refined technique for the extraction of the generation lifetime in single- and double-gate partially depleted SOI nMOSFETs. The model presented in this paper, based on the drain current switch-off transients, takes into account the influence of the laterally non-uniform channel doping, caused by the presence of the halo implanted region, and the amount of charge controlled by the drain and source junctions on the floating body effect when the channel length is reduced. The obtained results for single- gate (SG) devices are compared with two-dimensional numerical simulations and experimental data, extracted for devices fabricated in a 0.1 mu m SOI CMOS technology, showing excellent agreement. The improved model to determine the generation lifetime in double-gate (DG) devices beyond the considerations previously presented also consider the influence of the silicon layer thickness on the drain current transient. The extracted data through the improved model for DG devices were compared with measurements and two-dimensional numerical simulations of the SG devices also presenting a good adjustment with the channel length reduction and the same tendency with the silicon layer thickness variation.