Dynamic Visual Servoing With Chaos Control for Redundant Robots

This paper presents a new dynamic visual control system for redundant robots with chaos compensation. In order to implement the visual servoing system, a new architecture is proposed that improves the system maintainability and traceability. Furthermore, high performance is obtained as a result of parallel execution of the different tasks that compose the architecture. The control component of the architecture implements a new visual servoing technique for resolving the redundancy at the acceleration level in order to guarantee the correct motion of both end-effector and joints. The controller generates the required torques for the tracking of image trajectories. However, in order to guarantee the applicability of this technique, a repetitive path tracked by the robot-end must produce a periodic joint motion. A chaos controller is integrated in the visual servoing system and the correct performance is observed in low and high velocities. Furthermore, a method to adjust the chaos controller is proposed and validated using a real three-link robot.

Selective SWIFT-R. A Flexible Software-Based Technique for Soft Error Mitigation in Low-Cost Embedded Systems

Commercial off-the-shelf microprocessors are the core of low-cost embedded systems due to their programmability and cost-effectiveness. Recent advances in electronic technologies have allowed remarkable improvements in their performance. However, they have also made microprocessors more susceptible to transient faults induced by radiation. These non-destructive events (soft errors), may cause a microprocessor to produce a wrong computation result or lose control of a system with catastrophic consequences. Therefore, soft error mitigation has become a compulsory requirement for an increasing number of applications, which operate from the space to the ground level. In this context, this paper uses the concept of selective hardening, which is aimed to design reduced-overhead and flexible mitigation techniques. Following this concept, a novel flexible version of the software-based fault recovery technique known as SWIFT-R is proposed. Our approach makes possible to select different registers subsets from the microprocessor register file to be protected on software. Thus, design space is enriched with a wide spectrum of new partially protected versions, which offer more flexibility to designers. This permits to find the best trade-offs between performance, code size, and fault coverage. Three case studies have been developed to show the applicability and flexibility of the proposal.

A relaxation technique enhances psychological well-being and immune parameters in elderly people from a nursing home: A randomized controlled study

Background: The aging process involves a decline in immune functioning that renders elderly people more vulnerable to disease. In residential programs for the aged, it is vital to diminish their risk of disease, promote their independence, and augment their psychological well-being and quality of life. Methods: We performed a randomized controlled study, evaluating the ability of a relaxation technique based on Benson’s relaxation response to enhance psychological well-being and modulate the immune parameters of elderly people living in a geriatric residence when compared to a waitlist control group. The study included a 2-week intervention period and a 3-month follow-up period. The main outcome variables were psychological well-being and quality of life, biomedical variables, immune changes from the pre-treatment to post-treatment and follow-up periods. Results: Our findings reveal significant differences between the experimental and control groups in CD19, CD71, CD97, CD134, and CD137 lymphocyte subpopulations at the end of treatment. Furthermore, there was a decrease in negative affect, psychological discomfort, and symptom perception in the treatment group, which increased participants’ quality of life scores at the three-month follow-up. Conclusions: This study represents a first approach to the application of a passive relaxation technique in residential programs for the elderly. The method appears to be effective in enhancing psychological well-being and modulating immune activity in a group of elderly people. This relaxation technique could be considered an option for achieving health benefits with a low cost for residential programs, but further studies using this technique in larger samples of older people are needed to confirm the trends observed in the present study. Trial registration: International Standard Randomised Controlled Trial Number Register ISRCTN85410212.

Efficient Mitigation of Data and Control Flow Errors in Microprocessors

The use of microprocessor-based systems is gaining importance in application domains where safety is a must. For this reason, there is a growing concern about the mitigation of SEU and SET effects. This paper presents a new hybrid technique aimed to protect both the data and the control-flow of embedded applications running on microprocessors. On one hand, the approach is based on software redundancy techniques for correcting errors produced in the data. On the other hand, control-flow errors can be detected by reusing the on-chip debug interface, existing in most modern microprocessors. Experimental results show an important increase in the system reliability even superior to two orders of magnitude, in terms of mitigation of both SEUs and SETs. Furthermore, the overheads incurred by our technique can be perfectly assumable in low-cost systems.

S-SETA: Selective Software-Only Error-Detection Technique Using Assertions

Software-based techniques offer several advantages to increase the reliability of processor-based systems at very low cost, but they cause performance degradation and an increase of the code size. To meet constraints in performance and memory, we propose SETA, a new control-flow software-only technique that uses assertions to detect errors affecting the program flow. SETA is an independent technique, but it was conceived to work together with previously proposed data-flow techniques that aim at reducing performance and memory overheads. Thus, SETA is combined with such data-flow techniques and submitted to a fault injection campaign. Simulation and neutron induced SEE tests show high fault coverage at performance and memory overheads inferior to the state-of-the-art.