Temporal aspects of the VO2 response at the power output associated with VO2peak in well trained cyclists: Implications for interval training prescription

The power output achieved at peak oxygen consumption (VO2 peak) and the time this power can be maintained (i.e., Tmax) have been used in prescribing high-intensity interval training. In this context, the present study examined temporal aspects of the VO2 response to exercise at the cycling power that output well trained cyclists achieve their VO2 peak (i.e., Pmax). Following a progressive exercise test to determine VO2 peak, 43 well trained male cyclists (M age = 25 years, SD = 6; M mass = 75 kg SD = 7; M VO2 peak = 64.8 ml(.)kg(1.)min(-1), SD = 5.2) performed two Tmax tests 1 week apart.1. Values expressed for each participant are means and standard deviations of these two tests. Participants achieved a mean VO2 peak during the Tmax test after 176 s (SD = 40; = 74% of Tmax, SD = 12) and maintained it for 66 s (SD = 39; M = 26% of Tmax, SD = 12). Additionally they obtained mean 95 % of VO2 peak after 147 s (SD = 31; M = 62 % of Tmax, SD = 8) and maintained it for 95 s (SD = 38; M = 38 % of Tmax, SD = 8). These results suggest that 60-70% of Tmax is an appropriate exercise duration for a population of well trained cyclists to attain VO2 peak during exercise at Pmax. However due to intraparticipant variability in the temporal aspects of the VO2 response to exercise at Pmax, future research is needed to examine whether individual high-intensity interval training programs for well trained endurance athletes might best be prescribed according to an athlete's individual VO2 response to exercise at Pmax.

Test strategies on functionally partitioned module-based programmable architecture for base-band processing

A specialised reconfigurable architecture for telecommunication base-band processing is augmented with testing resources. The routing network is linked via virtual wire hardware modules to reduce the area occupied by connecting buses. The number of switches within the routing matrices is also minimised, which increases throughput without sacrificing flexibility. The testing algorithm was developed to systematically search for faults in the processing modules and the flexible high-speed routing network within the architecture. The testing algorithm starts by scanning the externally addressable memory space and testing the master controller. The controller then tests every switch in the route-through switch matrix by making loops from the shared memory to each of the switches. The local switch matrix is also tested in the same way. Next the local memory is scanned. Finally, pre-defined test vectors are loaded into local memory to check the processing modules. This algorithm scans all possible paths within the interconnection network exhaustively and reports all faults. Strategies can be inserted to bypass minor faults