Predicting the Paths of Peripherals: The Interaction of Identification and Future Possibilities

Two studies investigated how both degree of identification and the individual's position within the group influence aspects of group loyalty. The authors considered ingroup position in terms of both the individual's current position within a group and expectations concerning the likelihood that one's position might change., in the future. Peripheral group members learned that their acceptance by other group members would improve in the future or that they could expect rejection by other group members. Various indices of group loyalty (ingroup homogeneity, motivation to work for the group, and evaluation of a motivated group member) showed that when group members anticipated future rejection, the lower the identification the less loyal they were. In contrast, those who expected future acceptance were more loyal (more motivated to work for the group) the lower their identification. Current group behavior depends on both intragroup future expectations and level of identification.

Interface adaptor logic: A new model for interfacing peripherals in IP based designs

The introduction of standard on-chip buses has eased integration and boosted the production of IP functional cores. However, once an IP is bus specific retargeting to a different bus is time-consuming and tedious, and this reduces the reusability of the bus-specific IP. As new bus standards are introduced and different interconnection methods are proposed, this problem increases. Many solutions have been proposed, however these solutions either limit the IP block performance or are restricted to a particular platform. A new concept is presented that can connect IP blocks to a wide variety of interface architectures with low overhead. This is achieved through the use a special interface adaptor logic layer.

Implementation of a triple modular redundant FPGA based safety critical system for reliable software execution

This paper describes the implementation of a TMR (Triple Modular Redundant) microprocessor system on a FPGA. The system exhibits true redundancy in that three instances of the same processor system (both software and hardware) are executed in parallel. The described system uses software to control external peripherals and a voter is used to output correct results. An error indication is asserted whenever two of the three outputs match or all three outputs disagree. The software has been implemented to conform to a particular safety critical coding guideline/standard which is popular in industry. The system was verified by injecting various faults into it.