Practical parallel coset enumeration

Coset enumeration is a most important procedure for investigating finitely presented groups. We present a practical parallel procedure for coset enumeration on shared memory processors. The shared memory architecture is particularly interesting because such parallel computation is both faster and cheaper. The lower cost comes when the program requires large amounts of memory, and additional CPU's. allow us to lower the time that the expensive memory is being used. Rather than report on a suite of test cases, we take a single, typical case, and analyze the performance factors in-depth. The parallelization is achieved through a master-slave architecture. This results in an interesting phenomenon, whereby the CPU time is divided into a sequential and a parallel portion, and the parallel part demonstrates a speedup that is linear in the number of processors. We describe an early version for which only 40% of the program was parallelized, and we describe how this was modified to achieve 90% parallelization while using 15 slave processors and a master. In the latter case, a sequential time of 158 seconds was reduced to 29 seconds using 15 slaves.

An everyday nostalgia: Memory and the fictions of belonging

In 1984, George Orwell presented the future as a dystopian vision, where everyday existence was governed and redefined by an oppressive regime. Winston Smith's daily duties at the Ministry of Truth involved the invention, rewriting and erasing of fragments of history as a means of perpetuating contentment, uniformity and control. History, as Orwell described it in the novel 'was a palimpsest, scraped clean and reinscribed exactly as often as was necessary.' More that a quarter of a century after the publication of 1984, Michel Foucault discussed the cinematic representation and misrepresentation of French history and identity in terms of what he called the manipulation of 'popular memory'. In what was tantamount to a diluted version of Orwell's palimpsestic histories, Foucault stated that 'people are not shown what they were, but what they must remember having been.' This paper will investigate notions of memory, identity and the everyday through a discussion of the community of Celebration in Florida. Conceived in the 1990s, Celebration was designed around a fictionalised representation of pre 1940s small town America, using nostalgia for a mythologised past to create a sense of comfort, community and conformity among its residents. Adapting issues raised by Orwell, Foucault and Baudrillard, this paper will discuss the way in which architecture, like film and literature, can participate in what Foucault discussed as the manipulation of popular memory, inducing and exploiting a nostalgia for an everyday past that that never really existed.

Functionally partitioned module-based programmable architecture for wireless base-band processing

A specialised reconfigurable architecture is targeted at wireless base-band processing. It is built to cater for multiple wireless standards. It has lower power consumption than the processor-based solution. It can be scaled to run in parallel for processing multiple channels. Test resources are embedded on the architecture and testing strategies are included. This architecture is functionally partitioned according to the common operations found in wireless standards, such as CRC error correction, convolution and interleaving. These modules are linked via Virtual Wire Hardware modules and route-through switch matrices. Data can be processed in any order through this interconnect structure. Virtual Wire ensures the same flexibility as normal interconnects, but the area occupied and the number of switches needed is reduced. The testing algorithm scans all possible paths within the interconnection network exhaustively and searches for faults in the processing modules. The testing algorithm starts by scanning the externally addressable memory space and testing the master controller. The controller then tests every switch in the route-through switch matrix by making loops from the shared memory to each of the switches. The local switch matrix is also tested in the same way. Next the local memory is scanned. Finally, pre-defined test vectors are loaded into local memory to check the processing modules. This paper compares various base-band processing solutions. It describes the proposed platform and its implementation. It outlines the test resources and algorithm. It concludes with the mapping of Bluetooth and GSM base-band onto the platform.

The value of a small microkernel for dreamy memory and the RAMpage memory hierarchy

This paper explores potential for the RAMpage memory hierarchy to use a microkernel with a small memory footprint, in a specialized cache-speed static RAM (tightly-coupled memory, TCM). Dreamy memory is DRAM kept in low-power mode, unless referenced. Simulations show that a small microkernel suits RAMpage well, in that it achieves significantly better speed and energy gains than a standard hierarchy from adding TCM. RAMpage, in its best 128KB L2 case, gained 11% speed using TCM, and reduced energy 14%. Equivalent conventional hierarchy gains were under 1%. While 1MB L2 was significantly faster against lower-energy cases for the smaller L2, the larger SRAM's energy does not justify the speed gain. Using a 128KB L2 cache in a conventional architecture resulted in a best-case overall run time of 2.58s, compared with the best dreamy mode run time (RAMpage without context switches on misses) of 3.34s, a speed penalty of 29%. Energy in the fastest 128KB L2 case was 2.18J vs. 1.50J, a reduction of 31%. The same RAMpage configuration without dreamy mode took 2.83s as simulated, and used 2.39J, an acceptable trade-off (penalty under 10%) for being able to switch easily to a lower-energy mode.

Test strategies on functionally partitioned module-based programmable architecture for base-band processing

A specialised reconfigurable architecture for telecommunication base-band processing is augmented with testing resources. The routing network is linked via virtual wire hardware modules to reduce the area occupied by connecting buses. The number of switches within the routing matrices is also minimised, which increases throughput without sacrificing flexibility. The testing algorithm was developed to systematically search for faults in the processing modules and the flexible high-speed routing network within the architecture. The testing algorithm starts by scanning the externally addressable memory space and testing the master controller. The controller then tests every switch in the route-through switch matrix by making loops from the shared memory to each of the switches. The local switch matrix is also tested in the same way. Next the local memory is scanned. Finally, pre-defined test vectors are loaded into local memory to check the processing modules. This algorithm scans all possible paths within the interconnection network exhaustively and reports all faults. Strategies can be inserted to bypass minor faults

Effects of temporal association on recognition memory

The influence of temporal association on the representation and recognition of objects was investigated. Observers were shown sequences of novel faces in which the identity of the face changed as the head rotated. As a result, observers showed a tendency to treat the views as if they were of the same person. Additional experiments revealed that this was only true if the training sequences depicted head rotations rather than jumbled views; in other words, the sequence had to be spatially as well as temporally smooth. Results suggest that we are continuously associating views of objects to support later recognition, and that we do so not only on the basis of the physical similarity, but also the correlated appearance in time of the objects.

Remembering sport history: Narrative, social memory and the origins of the rugby league in Australia

This study examines the historiography of the origins of rugby league in Australia. By accepting the inclusive nature of representation of the past as found in social memory theory, a wide range of sources ranging from histories written by academics to annuals, yearbooks and newspaper books are consulted. These sources reveal that there are several competing and conflicting accounts of the emergence of rugby league in Australia. These divergent accounts are used to facilitate a discussion of the role of narrative in sport history This article argues that narrative is an integral, not optional, feature of the production of history and that the historography of the origins of rugby league highlight the problematic nature of objectivity in history and the unavoidable, impositionalist role of the historian.

Traditional architecture in the Pacific

Architecture of the Pacific covers a region of more than third of the earth’s surface. The sparse Pacific population spreads over some 30 000 islands, which graduate in size from small atolls to the largest island, Australia, a continent. Pacific architecture can be studied as four cultural units: Micronesia, Polynesia, Melanesia, and Australasia (Australia and New Zealand). While many of the islands of Micronesia lie above the Equator, the remaining Pacific islands are in the southern hemisphere. With the exception of Australia, most of the islands have a warm and humid tropical climate with high rainfalls and lush vegetation. Some islands lie in the cyclonic and earthquake belts. Two distinct racial groups settled the region. The indigenous people, the Micronesians, Melanesians, Polynesians, Australian Aborigines and New Zealand Maoris, migrated from Asia thousands of years ago. The second group, the recent immigrants, were Europeans, who occupied the region during the last two centuries, and pockets of Asians brought in by colonial administrations as labourers during the early twentieth century.