8 resultados para K-BAND

em University of Queensland eSpace - Australia


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A specialised reconfigurable architecture is targeted at wireless base-band processing. It is built to cater for multiple wireless standards. It has lower power consumption than the processor-based solution. It can be scaled to run in parallel for processing multiple channels. Test resources are embedded on the architecture and testing strategies are included. This architecture is functionally partitioned according to the common operations found in wireless standards, such as CRC error correction, convolution and interleaving. These modules are linked via Virtual Wire Hardware modules and route-through switch matrices. Data can be processed in any order through this interconnect structure. Virtual Wire ensures the same flexibility as normal interconnects, but the area occupied and the number of switches needed is reduced. The testing algorithm scans all possible paths within the interconnection network exhaustively and searches for faults in the processing modules. The testing algorithm starts by scanning the externally addressable memory space and testing the master controller. The controller then tests every switch in the route-through switch matrix by making loops from the shared memory to each of the switches. The local switch matrix is also tested in the same way. Next the local memory is scanned. Finally, pre-defined test vectors are loaded into local memory to check the processing modules. This paper compares various base-band processing solutions. It describes the proposed platform and its implementation. It outlines the test resources and algorithm. It concludes with the mapping of Bluetooth and GSM base-band onto the platform.

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The design of an X-band tray-type spatial power combiner, which employs uniplanar quasi-Yagi antennas (QYAs) for receiving and transmitting signals by individual amplifiers, is presented. Passive and active varieties of a seven-tray power-combining structure that includes two hard horns for uniform signal launching and combining across the tray stack are developed and measured. In order to compensate for nonuniform phase across the stack, which is caused by the nonplanar wave front of the horn antennas, Schiffman phase shifters are implemented in individual trays. The experimental-results show an improved performance of the investigated tray-type power combiner when the proposed phase-error compensation is implemented. (C) 2004 Wiley Periodicals, Inc.

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The design of dual-band 2.45/5.2 GHz antenna for an acces point of a Wireless Local Area Network (LAN) is presented. The proposed antenna is formed by a Radial Line Slot Array (RLSA) operating at 2.4 GHz and a Microstrip patch working at 5.2 GHz, both featuring circular polarization. The design of this antenna system is accomplished using commercially available Finite Element software. High Frequency Structure Simulator (HFSS) of Ansoft and an in-house developed iteration procedure. The performance of the designed antenna is assessed in terms of return loss (RL), radiation pattern and polarization purity in the two frequency bands.

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Banded defects are often found in high-pressure die castings. These bands can contain segregation, porosity, and/or tears, and changing casting conditions and alloy are known to change the position and make-up of the bands. Due to the complex, dynamic nature of the high-pressure die-casting (HPDC) process, it is very difficult to study the effect of individual parameters on band formation. In the work presented here, bands of segregation similar to those found in cold-chamber HPDC aluminum alloys were found in laboratory gravity die castings. Samples were cast with a range of fraction solids from 0 to 0.3 and the effect of die temperature and external solid fraction on segregation bands was investigated. The results are considered with reference to the theological properties of the filling semisolid metal and a formation mechanism for bands is proposed by considering flow past a solidifying immobile wall layer.

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Design and development of a photonic bandgap (PBG)-assisted shared-aperture dual-band orthogonal aperture-fed rectangular microstrip patch antenna element, which is suitable for a portable very small aperture terminal (VSAT), are presented in this paper. The dual-band dual-polarized antenna element achieves 21% input impedance bandwidth at the S- and C-bands. A comparison of the antenna with and without 2D PBG grids shows that the inclusion of PBG structures (PBGSs) improves the antenna performances. (c) 2005 Wiley Periodicals, Inc.

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The design of an antenna that combines a radial line slot array and a circular patch to operate as a dual band (2.4/5.2 GHz) antenna at the access point of a WLAN is presented. The design has been accomplished using commercially available Ansoft HFSS and in-house developed software. The designed antenna shows good performance in terms of return losses, radiation pattern and circular polarization in the two, 2.4 and 5.2 GHz, frequency bands. Due to its good electrical performance and a relatively low profile and low developmental cost, it should be found attractive for use as an access point antenna for dual band operation.

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The design of a dual-band 2.45/5.2 GHz antenna for an access point of a wireless local area network (WLAN) is presented. The proposed antenna is formed by an assembly of a radial line slot array (RLSA) operating at 2.4 GHz and a microstrip patch working at 5.2 GHz. The design of this antenna system is accomplished using commercially available finite element software, high frequency structure simulator (HFSS), of Ansoft. The performance of the designed antenna is assessed in terms of return loss (RL), radiation pattern and polarization purity in the two investigated frequency bands.

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A specialised reconfigurable architecture for telecommunication base-band processing is augmented with testing resources. The routing network is linked via virtual wire hardware modules to reduce the area occupied by connecting buses. The number of switches within the routing matrices is also minimised, which increases throughput without sacrificing flexibility. The testing algorithm was developed to systematically search for faults in the processing modules and the flexible high-speed routing network within the architecture. The testing algorithm starts by scanning the externally addressable memory space and testing the master controller. The controller then tests every switch in the route-through switch matrix by making loops from the shared memory to each of the switches. The local switch matrix is also tested in the same way. Next the local memory is scanned. Finally, pre-defined test vectors are loaded into local memory to check the processing modules. This algorithm scans all possible paths within the interconnection network exhaustively and reports all faults. Strategies can be inserted to bypass minor faults