A 64-point fourier transform chip for video motion compensation using phase correlation

Details of a new low power fast Fourier transform (FFT) processor for use in digital television applications are presented. This has been fabricated using a 0.6-µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-time video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8 × 8 mm and dissipates 1 W. The chip design is based on a novel VLSI architecture which has been derived from a first principles factorization of the discrete Fourier transform (DFT) matrix and tailored to a direct silicon implementation.

Fourier Transform using a Rotman Lens

In this paper, the design constraints that are required for a Rotman lens to realize discrete Fourier transform (DFT) amplitude and phase functionality are derived. A Fourier Rotman lens has been designed, fabricated and validated. The amplitude and phase response and the array pattern based on the CST™ results are validated with the theoretical DFT results. To the best of the authors' knowledge, this is the first Fourier Rotman lens to be fabricated and validated. The solution provided replaces multilayer Butler matrix solutions with a simple single layer microstrip technology.

Reuseable Silicon IP Cores for Discrete Wavelet Transform Applications

Architectures and methods for the rapid design of silicon cores for implementing discrete wavelet transforms over a wide range of specifications are described. These architectures are efficient, modular, scalable, and cover orthonormal and biorthogonal wavelet transform families. They offer efficient hardware utilization by exploiting a number of core wavelet filter properties and allow the creation of silicon designs that are highly parameterized, including in terms of wavelet type and wordlengths. Control circuitry is embedded within these systems allowing them to be cascaded for any desired level of decomposition without any interface glue logic. The time to produce chip designs for a specific wavelet application is typically less than a day and these are comparable in area and performance to handcrafted designs. They are also portable across a wide range of silicon foundries and suitable for field programmable gate array and programmable logic data implementation. The approach described has also been extended to wavelet packet transforms.

Forensic analysis of architectural finishes using Fourier transform infrared and Raman spectroscopy, Part I: The resin bases

The ability of Raman spectroscopy and Fourier transform infrared (FT-IR) microscopy to discriminate between resins used for the manufacture of architectural finishes was examined in a study of 39 samples taken from a commercial resin library. Both Raman and FT-IR were able to discriminate between different types of resin and both split the samples into several groups (six for FT-IR, six for Raman), each of which gave similar, but not identical, spectra. In addition, three resins gave unique Raman spectra (four in FTIR). However, approximately half the library comprised samples that were sufficiently similar that they fell into a single large group, whether classified using FT-IR or Raman, although the remaining samples fell into much smaller groups. Further sub-division of the FT-IR groups was not possible because the experimental uncertainty was of similar magnitude to the within-group variation. In contrast, Raman spectroscopy was able to further discriminate between resins that fell within the same groups because the differences in the relative band intensities of the resins, although small, were larger than the experimental uncertainty.

64-point Fourier transform chip for digital television applications

A 64-point Fourier transform chip is described that performs a forward or inverse, 64-point Fourier transform on complex two's complement data supplied at a rate of 13.5MHz and can operate at clock rates of up to 40MHz, under worst-case conditions. It uses a 0.6µm double-level metal CMOS technology, contains 535k transistors and uses an internal 3.3V power supply. It has an area of 7.8×8mm, dissipates 0.9W, has 48 pins and is housed in a 84 pin PLCC plastic package. The chip is based on a FFT architecture developed from first principles through a detailed investigation of the structure of the relevant DFT matrix and through mapping repetitive blocks within this matrix onto a regular silicon structure.