Hierarchical VHDL libraries for DSP ASIC design

Methods are presented for the rapid design of DSP ASICs based on the use of hierarchical VHDL libraries. These are portable across many silicon foundries and allow complex DSP silicon systems to be developed in a fraction of the time normally required. Resulting designs are highly competitive with ones created using conventional methods. The approach is illustrated by its application to ADPCM codec and DCT cores.

A Steganalysis System Utilizing Temporal Pixel Correlation Of HEVC Video

High Efficiency Video Coding (HEVC) is the most recent video codec coming after currently most popular H.264/MPEG4 codecs and has promising compression capabilities. It is conjectured that it will be a substitute for current video compression standards. However, to the best knowledge of the authors, none of the current video steganalysis methods designed or tested with HEVC video. In this paper, pixel domain steganography applied on HEVC video is targeted for the first time. Also, its the first paper that employs accordion unfolding transformation, which merges temporal and spatial correlation, in pixel domain video steganalysis. With help of the transformation, temporal correlation is incorporated into the system. Its demonstrated for three different feature sets that integrating temporal dependency substantially increased the detection accuracy.