Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A(vo)) and cut-off frequency (f(T)) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 mu A/mu m, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SIDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g(m)), transconductance-to-current ratio (g(m)/I-ds), Early voltage (V-EA), output conductance (g(ds)) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs. (C) 2007 Elsevier B.V. All rights reserved.

Characterizing multipartite symmetric Dicke states under the effects of noise

We study genuine multipartite entanglement (GME) in a system of n qubits prepared in symmetric Dicke states and subjected to the influences of noise. We provide general, setup-independent expressions for experimentally favorable tools such as fidelity- and collective spin-based entanglement witnesses, as well as entangled-class discriminators and multi-point correlation functions. Besides highlighting the effects of the environment on large qubit registers, we also discuss strategies for the robust detection of GME. Our work provides techniques and results for the experimental communities interested in investigating and characterizing multipartite entangled states by introducing realistic milestones for setup design and associated predictions.

A click chemistry approach to C3 symmetric, G-quadruplex stabilising ligands.

Described is the structure-based design and synthesis of a series of tris-triazole G-quadruplex binding ligands utilising the copper catalysed azide–alkyne ‘click’ reaction. The results of G-quadruplex stabilisation by the ligands are reported and discussed.

VLSI design and implementation of 2-D Inverse Discrete Wavelet Transform

This paper proposes a JPEG-2000 compliant architecture capable of computing the 2 -D Inverse Discrete Wavelet Transform. The proposed architecture uses a single processor and a row-based schedule to minimize control and routing complexity and to ensure that processor utilization is kept at 100%. The design incorporates the handling of borders through the use of symmetric extension. The architecture has been implemented on the Xilinx Virtex2 FPGA.