The Next Generation Transit Survey (NGTS)

The Next Generation Transit Survey (NGTS) is a new ground-based sky survey designed to find transiting Neptunes and super-Earths. By covering at least sixteen times the sky area of Kepler we will find small planets around stars that are sufficiently bright for radial velocity confirmation, mass determination and atmospheric characterisation. The NGTS instrument will consist of an array of twelve independently pointed 20cm telescopes fitted with red-sensitive CCD cameras. It will be constructed at the ESO Paranal Observatory, thereby benefiting from the very best photometric conditions as well as follow up synergy with the VLT and E-ELT. Our design has been verified through the operation of two prototype instruments, demonstrating white noise characteristics to sub-mmag photometric precision. Detailed simulations show that about thirty bright super-Earths and up to two hundred Neptunes could be discovered. Our science operations are due to begin in 2014.

Enhancing design space exploration by extending CPU/GPU specifications onto FPGAs

The design cycle for complex special-purpose computing systems is extremely costly and time-consuming. It involves a multiparametric design space exploration for optimization, followed by design verification. Designers of special purpose VLSI implementations often need to explore parameters, such as optimal bitwidth and data representation, through time-consuming Monte Carlo simulations. A prominent example of this simulation-based exploration process is the design of decoders for error correcting systems, such as the Low-Density Parity-Check (LDPC) codes adopted by modern communication standards, which involves thousands of Monte Carlo runs for each design point. Currently, high-performance computing offers a wide set of acceleration options that range from multicore CPUs to Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs). The exploitation of diverse target architectures is typically associated with developing multiple code versions, often using distinct programming paradigms. In this context, we evaluate the concept of retargeting a single OpenCL program to multiple platforms, thereby significantly reducing design time. A single OpenCL-based parallel kernel is used without modifications or code tuning on multicore CPUs, GPUs, and FPGAs. We use SOpenCL (Silicon to OpenCL), a tool that automatically converts OpenCL kernels to RTL in order to introduce FPGAs as a potential platform to efficiently execute simulations coded in OpenCL. We use LDPC decoding simulations as a case study. Experimental results were obtained by testing a variety of regular and irregular LDPC codes that range from short/medium (e.g., 8,000 bit) to long length (e.g., 64,800 bit) DVB-S2 codes. We observe that, depending on the design parameters to be simulated, on the dimension and phase of the design, the GPU or FPGA may suit different purposes more conveniently, thus providing different acceleration factors over conventional multicore CPUs.

On the performance of LDPC and turbo decoder architectures with unreliable memories

In this paper, we investigate the impact of faulty memory bit-cells on the performance of LDPC and Turbo channel decoders based on realistic memory failure models. Our study investigates the inherent error resilience of such codes to potential memory faults affecting the decoding process. We develop two mitigation mechanisms that reduce the impact of memory faults rather than correcting every single error. We show how protection of only few bit-cells is sufficient to deal with high defect rates. In addition, we show how the use of repair-iterations specifically helps mitigating the impact of faults that occur inside the decoder itself.

Review of João M. Cabrita, Mozambique. The Tortuous Road to Democracy.

Book review in Lusotopie, 2002, no.1 of João M. CABRITA, Mozambique. The Tortuous Road to Democracy, Basingstoke (G.-B.) et New York (E.U.A.), Palgrave (St. Martin’s Press), 2000, 311p., ISBN 0-333-92001-5.