Simulation of a collisionless planar electrostatic shock in a proton-electron plasma with a strong initial thermal pressure change

The localized deposition of the energy of a laser pulse, as it ablates a solid target, introduces high thermal pressure gradients in the plasma. The thermal expansion of this laser-heated plasma into the ambient medium (ionized residual gas) triggers the formation of non-linear structures in the collisionless plasma. Here an electron-proton plasma is modelled with a particle-in-cell simulation to reproduce aspects of this plasma expansion. A jump is introduced in the thermal pressure of the plasma, across which the otherwise spatially uniform temperature and density change by a factor of 100. The electrons from the hot plasma expand into the cold one and the charge imbalance drags a beam of cold electrons into the hot plasma. This double layer reduces the electron temperature gradient. The presence of the low-pressure plasma modifies the proton dynamics compared with the plasma expansion into a vacuum. The jump in the thermal pressure develops into a primary shock. The fast protons, which move from the hot into the cold plasma in the form of a beam, give rise to the formation of phase space holes in the electron and proton distributions. The proton phase space holes develop into a secondary shock that thermalizes the beam.

Numerical simulation of separation factor of NaCl in surface force pore flow model

This work deals with modelling and experimental verification of desalination theory (surface force pore flow) . The work has direct application in desalination of sea water.

6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

The impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/sigma) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM similar to 162 mV, I-wr similar to 35 mu A and low I-leak similar to 70 pA at V-DD = 0.6 V, while maintaining SNM similar to 30% V-DD over the supply voltage (V-DD) range of 0.4-0.9 V.